XC61H
Series
Voltage Detector with Delay Circuit Built-In
ETR0212-004
■GENERAL
DESCRIPTION
The XC61H series is a highly accurate, low power consumption CMOS voltage detector with a delay circuit. Detect voltage is
accurate with minimal temperature drift. Output configurations are available in both CMOS and N-channel open drain.
Since the full delay circuit is built-in, an external delay-time capacitor is not necessary so that high density mounting is possible.
■APPLICATIONS
●
Microprocessor reset circuitry
●
System battery life and charge voltage monitors
●
Memory battery back-up circuits
●
Power-on reset circuits
●
Power failure detection
●
Delay circuitry
■FEATURES
Detect Voltage Accuracy
: ± 2%
Low Power Consumption
: 1.0μA(TYP.)[ V
IN
=2.0V ]
: 1.6V ~ 6.0V (0.1V increments)
Detect Voltage Range
Operating Voltage Range
: 0.7V ~ 10.0V
Detect Voltage Temperature Characteristics
: ±100ppm/℃(TYP.)
Built-In Release Delay time
: 1ms (MIN.)
50ms (MIN.)
80ms (MIN.)
Output Configuration
: N-ch open drain output or CMOS
Operating Ambient Temperature
: 30℃∼+80℃
Package
: SOT-23
Environmentally Friendly
: EU RoHS Compliant, Pb Free
■TYPICAL
APPLICATION CIRCUITS
■TYPICAL
PERFORMANCE
CHARACTERISTICS
μP
V
IN
R pull
●Release
Delay Time (t
DR
) vs. Ambient Temperature
ＸＣ６１ＨＣ３０１２
Release Delay Time: t
DR
(ms)
RESETB
2
V
IN
3
V
SS
1
RESETB
INPUT
V
SS
XC61HN series
Rpull is
Not necessary with CMOS output products
not necessary with CMOS output products
Ambient Temperature: Ta (℃)
1/13
XC61H
Series
■OPERATIONAL
EXPLANATION
●CMOS
output
An input voltage V
IN
starts higher than the release voltage V
DR
. Then, V
IN
voltage will gradually fall. When V
IN
voltage is
higher than detect voltage V
DF
, output voltage RESETB is equal to the V
IN
voltage.
*Note that high impedance exists at RESETB with the N-channel open drain output configuration. If the RESETB pin is
pulled up, RESETB will be equal to the pull up voltage.
②
When V
IN
falls below V
DF
, RESETB will be equal to ground voltage V
SS
level (detect state).
* Note that this also applies to N-channel open drain output configurations.
③
When VI
N
falls to a level below that of the minimum operating voltage V
MIN,
output will become unstable.
*When the output pin is generally pulled up with N-channel open drain output configurations, output will be equal to pull
up voltage.
④
When V
IN
rises above the V
SS
level (excepting levels lower than minimum operating voltage), RESETB will be equal to
V
SS
until V
IN
reaches the V
DR
level.
⑤
Although V
IN
will rise to a level higher than V
DR
, RESETB maintains ground voltage level via the delay circuit.
⑥
After taking a release delay time, V
IN
voltage will be output at the RESETB pin.
*High impedance exists with the N-channel open drain output configuration and that voltage will be dependent on pull up.
①
Notes:
1. The difference between V
DR
and V
DF
represents the hysteresis width.
2. Release delay time (
t
DR
) represents the time it takes until when V
IN
voltage appears at RESETB pin once the input
voltage has exceeded the V
DR
level.
●Timing
Chart
Output Voltage (RESETB)
Release Delay Time (t
DR
)
4/13
XC61H
Series
■NOTES
ON USE
1. Please use this IC within the stated maximum ratings. For temporary, transitional voltage drop or voltage rising
phenomenon, the IC is liable to malfunction should the ratings be exceeded.
2. When a resistor is connected between the V
IN
pin and the power supply with CMOS output configurations, irregular
oscillation may occur as a result of voltage drops at R
IN
if load current (I
OUT
) exists. It is therefore recommend that no
resistor be added. (refer to Figure 1 below)
3. When a resistor (R
IN
) is connected between the V
IN
pin and the power supply with CMOS output configurations,
irrespective of N-ch open drain output configurations, oscillation may occur as a result of shoot-through current at the time
of voltage release even if load current (I
OUT
) does not exist. (refer to Figure 2 below)
4. If a resistor (R
IN
) must be used, then please use with as small a level of input impedance as possible in order to control the
occurrences of oscillation as described above. Further, please ensure that R
IN
is less than 10kΩ and that C
IN
is more than
0.1μF, please test with the actual device. However, N-ch open drain output only. (Figure 1).
5. With a resistor RIN connected between the V
IN
pin and the power supply, the V
IN
pin voltage will be getting lower than the
power supply voltage as a result of the IC's supply current flowing through the V
IN
pin.
6. Depending on circuit's operation, release delay time of this IC can be widely changed due to upper limits or lower limits of
operational ambient temperature.
7. Torex places an importance on improving our products and its reliability.
However, by any possibility, we would request user fail-safe design and post-aging treatment on system or equipment.
●
Irregular Oscillations
(1) Irregular oscillation as a result of load current with the CMOS output configuration:
When the voltage applied at power supply, release operations commence and the detector's output voltage
increases. Load current (I
OUT
) will flow through R
L
. Because a voltage drop (R
IN
x I
OUT
) is produced at the R
IN
resistor,
located between the power supply and the V
IN
pin, the load current will flow via the IC's V
IN
pin. The voltage drop will
also lead to a fall in the voltage level at the V
IN
pin. When the V
IN
pin voltage level falls below the detect voltage level,
detect operations will commence. Following detect operations, load current flow will cease and since voltage drop at
R
IN
will disappear, the voltage level at the V
IN
pin will rise and release operations will begin over again.
Irregular oscillation may occur with this "release - detect - release" repetition.
Further, this condition will also appear via means of a similar mechanism during detect operations.
(2) Irregular oscillation as a result of shoot-through current:
Since the XC61H series are CMOS IC
S
, shoot-through current will flow when the IC's internal circuit switching
operates (during release and detect operations). Consequently, irregular oscillation is liable to occur during release
voltage operations as a result of output current which is influenced by this shoot-through current (Figure 3).
Since hysteresis exists during detect operations, irregular oscillation is unlikely to occur.
XC61HC Series
XC61HN Series
Power Supply
Power Supply
図 1．入力抵抗を入れた時の回路例
Figure 1 Use of input resistor R
IN
5/13
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
