电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

CY62148DV30LL-55SXIT

产品描述SRAM 4Mb 3V 55ns 256K x 8 LP SRAM
产品类别存储   
文件大小428KB,共15页
制造商Cypress(赛普拉斯)
下载文档 详细参数 全文预览

CY62148DV30LL-55SXIT在线购买

供应商 器件名称 价格 最低购买 库存  
CY62148DV30LL-55SXIT - - 点击查看 点击购买

CY62148DV30LL-55SXIT概述

SRAM 4Mb 3V 55ns 256K x 8 LP SRAM

CY62148DV30LL-55SXIT规格参数

参数名称属性值
产品种类
Product Category
SRAM
制造商
Manufacturer
Cypress(赛普拉斯)
RoHSDetails
Memory Size4 Mbit
Organization512 k x 8
Access Time55 ns
接口类型
Interface Type
Parallel
电源电压-最大
Supply Voltage - Max
3.6 V
电源电压-最小
Supply Voltage - Min
2.2 V
Supply Current - Max10 mA
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 85 C
安装风格
Mounting Style
SMD/SMT
封装 / 箱体
Package / Case
SOIC-32
系列
Packaging
Reel
数据速率
Data Rate
SDR
Memory TypeSDR
Moisture SensitiveYes
Number of Ports1
工厂包装数量
Factory Pack Quantity
1000
类型
Type
Asynchronous
单位重量
Unit Weight
0.027023 oz

文档预览

下载PDF文档
CY62148DV30
4-Mbit (512 K × 8) MoBL
®
Static RAM
4-Mbit (512 K × 8) MoBL
®
Static RAM
Features
Functional Description
The CY62148DV30
[1]
is a high-performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL
) in portable
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption. The device can be put into standby mode reducing
power consumption when deselected (CE HIGH).The eight input
and output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when:
Temperature Ranges
Industrial: –40 °C to 85 °C
Very high speed: 55 ns
Wide voltage range: 2.20 V–3.60 V
Pin-compatible with CY62148CV25, CY62148CV30 and
CY62148CV33
Ultra low active power
Typical active current: 1.5 mA at f = 1 MHz
Typical active current: 8 mA at f = f
max
(55-ns speed)
Ultra low standby power
Easy memory expansion with CE, and OE features
Automatic power-down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
Available in Pb-free 32-pin Small-outline integrated circuit
(SOIC package)
Deselected (CE HIGH)
Outputs are disabled (OE HIGH)
When the write operation is active(CE LOW and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
)
is then written into the location specified on the address pins (A
0
through A
18
).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins will appear on the I/O pins.
For a complete list of related documentation, click
here.
Logic Block Diagram
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
CE
WE
OE
Data in Drivers
I/O
0
I/O
1
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
512K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
Note
1. For best practice recommendations, refer to the Cypress application note “System
Design Guidelines”
on
http://www.cypress.com.
A
13
A
14
A
15
A
16
A
17
A
18
Cypress Semiconductor Corporation
Document Number: 38-05341 Rev. *I
198 Champion Court
San Jose
,
CA 95134-1709
• 408-943-2600
Page 1 of 15

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 2157  1592  775  1923  6  25  29  9  14  46 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved