Philips Semiconductors
Product specification
3.3V 16-bit transparent D-type latch (3-State)
74LVT16373A
FEATURES
•
16-bit transparent latch
•
3-State buffers
•
Output capability: +64mA/-32mA
•
TTL input and output switching levels
•
Input and output interface capability to systems at 5V supply
•
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
DESCRIPTION
The 74LVT16373A is a high-performance BiCMOS product
designed for V
CC
operation at 3.3V.
This device is a 16-bit transparent D-type latch with non-inverting
3-State bus compatible outputs. The device can be used as two
8-bit latches or one 16-bit latch. When enable (E) input is High, the
Q outputs follow the data (D) inputs. When enable is taken Low, the
Q outputs are latched at the levels of the D inputs one setup time
prior to the High-to-Low transition.
•
Live insertion/extraction permitted
•
Power-up reset
•
Power-up 3-State
•
No bus current loading when output is tied to 5V bus
•
Latch-up protection exceeds 500mA per JEDEC Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
nDx to nQx
Input capacitance
Output capacitance
Total supply current
C
L
= 50pF;
V
CC
= 3.3V
V
I
= 0V or 3.0V
Outputs disabled; V
O
= 0V or 3.0V
Outputs disabled; V
CC
= 3.6V
CONDITIONS
T
amb
= 25°C
TYPICAL
1.9
3
9
70
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVT16373A DL
74LVT16373A DGG
NORTH AMERICA
VT16373A DL
VT16373A DGG
DWG NUMBER
SOT370-1
SOT362-1
LOGIC SYMBOL
47
46
44
43
41
40
38
37
PIN DESCRIPTION
PIN NUMBER
47, 46, 44, 43, 41, 40, 38, 37,
36, 35, 33, 32, 30, 29, 27, 26
SYMBOL
1D0 – 1D7
2D0 – 2D7
1Q0 – 1Q7
2Q0 – 2Q7
1OE, 2OE
FUNCTION
Data inputs
Data outputs
Output enable
inputs
(active-Low)
Enable inputs
(active-High)
Ground (0V)
Positive
supply voltage
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
48
1
1LE
1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
2, 3, 5, 6, 8, 9, 11, 12, 13,
14, 16, 17, 19, 20, 22, 23
1, 24
2
36
3
35
5
33
6
32
8
30
9
29
11
27
12
26
48, 25
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
1E, 2E
GND
V
CC
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7
25
24
2LE
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
13
14
16
17
19
20
22
23
SA00044
1998 Feb 19
2
853-1780 18989
Philips Semiconductors
Product specification
3.3V 16-bit transparent D-type latch (3-State)
74LVT16373A
FUNCTION TABLE
INPUTS
nOE
L
L
L
L
L
H
H
H =
h =
L =
l =
NC=
X =
Z =
↓
=
nE
H
H
↓
↓
L
L
H
nDx
L
H
l
h
X
X
nDx
INTERNAL
REGISTER
L
H
L
H
NC
NC
nDx
OUTPUTS
OPERATING MODE
nQ0 – nQ7
L
H
L
H
NC
Z
Z
Enable and read register
Latch and read register
Hold
Disable outputs
High voltage level
High voltage level one set-up time prior to the High-to-Low E transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low E transition
No change
Don’t care
High impedance “off ” state
High-to-Low E transition
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Output in High state
Storage temperature range
–64
–65 to +150
°C
V
O
< 0
Output in Off or High state
Output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +7.0
–50
–0.5 to +7.0
128
mA
UNIT
V
mA
V
mA
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Input voltage
High-level output current
Low-level output current
Low-level output current; current duty cycle
≤
50%; f
≥
1kHz
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
–40
PARAMETER
LIMITS
MIN
2.7
0
2.0
0.8
–32
32
64
10
+85
ns/V
°C
MAX
3.6
5.5
UNIT
V
V
V
V
mA
mA
1998 Feb 19
4
Philips Semiconductors
Product specification
3.3V 16-bit transparent D-type latch (3-State)
74LVT16373A
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
V
IK
V
OH
PARAMETER
Input clamp voltage
High-level output voltage
TEST CONDITIONS
V
CC
= 2.7V; I
IK
= –18mA
V
CC
= 2.7 to 3.6V; I
OH
= –100µA
V
CC
= 2.7V; I
OH
= –8mA
V
CC
= 3.0V; I
OH
= –32mA
V
CC
= 2.7V; I
OL
= 100µA
V
CC
= 2.7V; I
OL
= 24mA
V
OL
Low–level output voltage
V
CC
= 3.0V; I
OL
= 16mA
V
CC
= 3.0V; I
OL
= 32mA
V
CC
= 3.0V; I
OL
= 64mA
V
RST
Power-up output Low voltage
5
V
CC
= 3.6V; I
O
= 1mA; V
I
= GND or V
CC
V
CC
= 3.6V; V
I
= V
CC
or GND
I
I
In ut
Input leakage current
V
CC
= 0 or 3.6V; V
I
= 5.5V
V
CC
= 3.6V; V
I
= V
CC
V
CC
= 3.6V; V
I
= 0
I
OFF
I
HOLD
Output off current
Bus Hold current D inputs
7
Current into an output in the
High state when V
O
> V
CC
Power up/down 3-State output
current
3
3-State output High current
3-State output Low current
Quiescent supply current
Additional supply current per
input pin
2
V
CC
= 0V; V
I
or V
O
= 0 to 4.5V
V
CC
= 3V; V
I
= 0.8V
V
CC
= 3V; V
I
= 2.0V
V
CC
= 0V to 3.6V; V
CC
= 3.6V
I
EX
I
PU/PD
I
OZH
I
OZL
I
CCH
I
CCL
I
CCZ
∆I
CC
V
O
= 5.5V; V
CC
= 3.0V
V
CC
≤
1.2V; V
O
= 0.5V to V
CC
; V
I
= GND or V
CC
;
OE/OE = Don’t care
V
CC
= 3.6V; V
O
= 3.0V; V
I
= V
IH
or V
IL
V
CC
= 3.6V; V
O
= 0.5V; V
I
= V
IH
or V
IL
V
CC
= 3.6V; Outputs High, V
I
= GND or V
CC,
I
O =
0
V
CC
= 3.6V; Outputs Low, V
I
= GND or V
CC,
I
O =
0
V
CC
= 3.6V; Outputs Disabled; V
I
= GND or V
CC,
I
O =
0
6
V
CC
= 3V to 3.6V; One input at V
CC
-0.6V,
Other inputs at V
CC
or GND
75
–75
±500
50
1
0.5
0.5
0.07
4.0
0.07
0.1
125
±100
5
–5
0.12
6
0.12
0.2
mA
mA
µA
µA
µA
Data
pins
4
ins
Control pins
V
CC
-0.2
2.4
2.0
Temp = -40°C to +85°C
MIN
TYP
1
–.85
V
CC
2.5
2.3
0.07
0.3
0.25
0.3
0.4
0.1
0.1
0.4
0.1
-0.4
0.1
135
-135
µA
0.2
0.5
0.4
0.5
0.55
0.55
±1
10
1
-5
±100
µA
µA
V
V
V
MAX
–1.2
V
UNIT
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND.
3. This parameter is valid for any V
CC
between 0V and 1.2V with a transition time of up to 10msec. From V
CC
= 1.2V to V
CC
= 3.3V
±
0.3V a
transition time of 100µsec is permitted. This parameter is valid for T
amb
= 25°C only.
4. Unused pins at V
CC
or GND.
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
6. I
CCZ
is measured with outputs pulled to V
CC
or GND.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 19
5
ST传感器与低功耗无线技术论坛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
