CY28410
Clock Generator for Intel
®
Grantsdale Chipset
Features
• Compliant with Intel
CK410
• Supports Intel P4 and Tejas CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 48 MHz USB clocks
CPU
x2 / x3
SRC
x6 / x7
PCI
x9
REF
x1
DOT96
x1
USB_48
x1
• 33 MHz PCI clock
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
Block Diagram
XIN
XOUT
Pin Configuration
VDD_PCI
VSS_PCI
PCI3
VDD_CPU
PCI4
CPUT[0:1], CPUC[0:1],
CPU(T/C)2_ITP]
PCI5
VDD_SRC
VSS_PCI
SRCT[1:6], SRCC[1:6]
VDD_PCI
PCIF0/ITP_EN
PCIF1
PCIF2
VDD_PCI
VDD_48
PCI[0:5]
USB_48
VDD_PCIF
PCIF[0:2]
VSS_48
DOT96T
DOT96C
VDD_48 MHz
FS_B/TEST_MODE
DOT96T
VTT_PWRGD#/PD
DOT96C
FS_A
USB_48
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
SRC4-SATAT
SRC4_SATAC
VDD_SRC
VDD_REF
REF
XTAL
OSC
PLL1
PLL Ref Freq
Divider
Network
FS_[C:A]
VTT_PWRGD#
IREF
PD
PLL2
SDATA
SCLK
I
2
C
Logic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI2
PCI1
PCI0
FS_C/TEST_SEL
REF
VSS_REF
XIN
XOUT
VDD_REF
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
VDD_SRC
SRCT6
SRCC6
SRCT5
SRCC5
VSS_SRC
56 SSOP/TSSOP
CY28410
........................ Document #: 38-07593 Rev. *C Page 1 of 17
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
CY28410
Pin Definitions
Pin No.
44,43,41,40
36,35
Name
CPUT/C
Type
O, DIF
Differential CPU clock outputs.
Description
CPUT2_ITP/SRCT7, O, DIF
Selectable Differential CPU or SRC clock output.
CPUC2_ITP/SRCC7
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
DOT96T, DOT96C
FS_A
FS_B/TEST_MODE
O, DIF
Fixed 96-MHz clock output.
I
I
3.3V tolerant input for CPU frequency selection.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Hi-Z when
in test mode
0 = Hi-Z,1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
3.3V tolerant input for CPU frequency selection.
Selects test mode if pulled
to V
IHFS_C
when VTT_PWRGD# is asserted low.
Refer to DC Electrical Specifications table for
V
ILFS_C
,V
IMFS_C
,V
IHFS_C
specifi-
cations.
A Precision resistor is attached to this pin, which is connected to the internal
current reference.
14,15
18
16
53
FS_C/TEST_SEL
I
39
IREF
I
54,55,56,3,4,5 PCI
9,10
8
52
46
47
26,27
PCIF
PCIF0/ITP_EN
REF
SCLK
SDATA
SRC4_SATAT,
SRC4_SATAC
O, SE
33-MHz clocks.
O, SE
33-MHz clocks.
I/O, SE
33-MHz clock/CPU2 select
(sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
O, SE
Reference clock.
3.3V 14.318 MHz clock output.
I
I/O
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
O, DIF
Differential serial reference clock.
recommended output for SATA.
O, DIF
Differential serial reference clocks.
19,20,22,23,2 SRCT/C
4,25,31,30,33,
32
12
11
42
1,7
48
21,28,34
37
13
45
2,6
51
29
38
17
USB_48
VDD_48
VDD_CPU
VDD_PCI
VDD_REF
VDD_SRC
VDDA
VSS_48
VSS_CPU
VSS_PCI
VSS_REF
VSS_SRC
VSSA
VTT_PWRGD#/PD
I/O, SE
Fixed 48 MHz clock output.
PWR
PWR
PWR
PWR
PWR
PWR
GND
GND
GND
GND
GND
GND
I, PU
3.3V power supply for outputs.
3.3V power supply for outputs.
3.3V power supply for outputs.
3.3V power supply for outputs.
3.3V power supply for outputs.
3.3V power supply for PLL.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for PLL.
3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A,
FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD#
(active low) assertion, this pin becomes a realtime input for asserting
power-down (active high)
14.318-MHz Crystal Input
50
49
XIN
XOUT
I
O, SE
14.318-MHz Crystal Output
........................Document #: 38-07593 Rev. *C Page 2 of 17
CY28410
Frequency Select Pins (FS_A, FS_B and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
Table 1. Frequency Select Table FS_A, FS_B and FS_C
FS_C
MID
0
0
0
1
1
1
FS_B
0
0
1
0
0
1
1
FS_A
1
1
0
0
x
0
1
CPU
100 MHz
133 MHz
200 MHz
266 MHz
Hi-Z
REF/2
REF/2
SRC
100 MHz
100 MHz
100 MHz
100 MHz
Hi-Z
REF/8
REF/8
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
Hi-Z
REF/24
REF/24
REF0
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Hi-Z
REF
REF
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
Hi-Z
REF
REF
USB
48 MHz
48 MHz
48 MHz
48 MHz
Hi-Z
REF
REF
samples the FS_A, FS_B and FS_C input values. For all logic
levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B and FS_C transitions will be ignored, except in
test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface initial-
izes to their default setting upon power-up, and therefore use
of this interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for pow-
er management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-
set of the indexed byte is encoded in the command code, as
described in
Table 2.
The block write and block read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Block Read Protocol
Description
........................Document #: 38-07593 Rev. *C Page 3 of 17
CY28410
Table 3. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Bit
46
....
....
....
....
Description
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N –8 bits
Acknowledge from slave
Stop
Bit
38
46:39
47
55:48
56
....
....
....
....
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
Control Registers
Byte 0:Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
Reserved
Description
CPU[T/C]2_ITP/SRC[T/C]7 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]6 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Reserved, Set = 1
........................Document #: 38-07593 Rev. *C Page 4 of 17
CY28410
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
0
1
1
0
Name
PCIF0
DOT_96T/C
USB_48
REF
Reserved
CPU[T/C]1
CPU[T/C]0
CPUT/C
SRCT/C
PCIF
PCI
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
REF Output Enable
0 = Disabled, 1 = Enabled
Reserved
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Description
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
PCIF2
PCIF1
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Description
Byte 3: Control Register 3
Bit
7
6
5
4
3
2
@Pup
0
0
0
0
0
0
Name
SRC7
SRC6
SRC5
SRC4
SRC3
SRC2
Description
Allow control of SRC[T/C]7 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]6 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]5 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]4 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]3 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
........................Document #: 38-07593 Rev. *C Page 5 of 17
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