Datasheet> 器件分类 > 无线/射频/通信> 电信电路> SX1231IMLTRT

SX1231IMLTRT: 产品描述Tactile Switches Top Actuated w/o boss w/o ground; 产品类别无线/射频/通信电信电路; 文件大小2MB，共88页; 制造商SEMTECH; 官网地址http://www.semtech.com; 标准

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SX1231IMLTRT在线购买

供应商	器件名称	价格	最低购买	库存
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SX1231IMLTRT概述

Tactile Switches Top Actuated w/o boss w/o ground

SX1231IMLTRT规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	SEMTECH
零件包装代码	QFN
包装说明	HVQCCN, LCC24,.19SQ,25
针数	24
Reach Compliance Code	compliant
JESD-30 代码	S-XQCC-N24
JESD-609代码	e3
长度	5 mm
湿度敏感等级	2
功能数量	1
端子数量	24
最高工作温度	85 °C
最低工作温度	-40 °C
封装主体材料	UNSPECIFIED
封装代码	HVQCCN
封装等效代码	LCC24,.19SQ,25
封装形状	SQUARE
封装形式	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	3.3 V
认证状态	Not Qualified
筛选级别	AEC-Q100
座面最大高度	1 mm
标称供电电压	3.3 V
表面贴装	YES
电信集成电路类型	TELECOM CIRCUIT
温度等级	INDUSTRIAL
端子面层	Matte Tin (Sn) - annealed
端子形式	NO LEAD
端子节距	0.65 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	5 mm

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SX1231

WIRELESS & SENSING PRODUCTS

DATASHEET

SX1231 Transceiver

Low Power Integrated UHF Transceiver

VBAT1&2

VR_ANA

VR_DIG

Oscillator

Σ/Δ

Modulators

Demodulator &

Bit Synchronizer

Decimation and

& Filtering

RESET

Power Distribution System

LNA

Single to

Differential

Mixers

RFIO

Control Registers - Shift Registers - SPI Interface

Packet Engine & 66 Bytes FIFO

SPI

RSSI

GND

Division by

2, 4 or 6

AFC

RXTX

DIO0

DIO1

DIO2

DIO3

DIO4

DIO5

PA0

Ramp &

Control

Tank

Inductor

Interpolation

& Filtering

VR_PA

Loop

Filter

Frac-N PLL

Synthesizer

PA_BOOST

PA1&2

32 MHz

XTAL

GND

GENERAL DESCRIPTION

The SX1231 is a highly integrated RF transceiver capable of

operation over a wide frequency range, including the 433,

868 and 915 MHz license-free ISM (Industry Scientific and

Medical) frequency bands. Its highly integrated architecture

allows for a minimum of external components whilst

maintaining maximum design flexibility. All major RF

communication parameters are programmable and most of

them can be dynamically set. The SX1231 offers the unique

advantage of programmable narrow-band and wide-band

communication modes without the need to modify external

components. The SX1231 is optimized for low power

consumption while offering high RF output power and

channelized operation. TrueRF™ technology enables a low-

cost external component count (elimination of the SAW

filter) whilst still satisfying ETSI and FCC regulations.

KEY PRODUCT FEATURES



High Sensitivity: down to -120 dBm at 1.2 kbps

High Selectivity: 16-tap FIR Channel Filter

Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,

80 dB Blocking Immunity, no Image Frequency response

Low current: Rx = 16 mA, 100nA register retention

Programmable Pout: -18 to +17 dBm in 1dB steps

Constant RF performance over voltage range of chip

FSK Bit rates up to 300 kb/s

Fully integrated synthesizer with a resolution of 61 Hz

FSK, GFSK, MSK, GMSK and OOK modulations

Built-in Bit Synchronizer performing Clock Recovery

Incoming Sync Word Recognition

115 dB+ Dynamic Range RSSI

Automatic RF Sense with ultra-fast AFC

Packet engine with CRC, AES-128 and 66-byte FIFO

Built-in temperature sensor and Low Battery indicator

APPLICATIONS



Automated Meter Reading

Wireless Sensor Networks

Home and Building Automation

Wireless Alarm and Security Systems

Industrial Monitoring and Control

Wireless M-BUS

ORDERING INFORMATION

Part Number

SX1231IMLTRT

SX1231ITSTRT

Package

QFN24

TSSOP28

Delivery

Tape &

Reel

MOQ / Multiple

3000 pieces

2500 pieces

MARKETS

Europe: EN 300-220-1

North America: FCC Part 15.247, 15.249, 15.231

Narrow Korean and Japanese bands, Arib STD-T108



Page 1

Pb-free, Halogen free, RoHS/WEEE compliant product

TSSOP: NiPdAu plated

Rev. 7 - June 2013

Modulator

www.semtech.com

SX1231

WIRELESS & SENSING PRODUCTS

Table of contents

DATASHEET

Section

Page

General Description ............................................................................................................................................... 10

1.1.

1.2.

1.3.

Simplified Block Diagram ............................................................................................................................... 10

Pin and Marking Diagram ..............................................................................................................................11

Pin Description ...............................................................................................................................................12

ESD Notice .................................................................................................................................................... 13

Absolute Maximum Ratings ........................................................................................................................... 13

Operating Range............................................................................................................................................ 13

Chip Specification ..........................................................................................................................................14

Electrical Characteristics ....................................................................................................................................... 13

2.1.

2.2.

2.3.

2.4.

2.4.1. Power Consumption .................................................................................................................................. 14

2.4.2. Frequency Synthesis................................................................................................................................. 14

2.4.3. Receiver .................................................................................................................................................... 15

2.4.4. Transmitter ................................................................................................................................................ 16

2.4.5. Digital Specification ...................................................................................................................................17

Chip Description .................................................................................................................................................... 18

3.1.

3.2.

3.3.

Power Supply Strategy .................................................................................................................................. 18

Low Battery Detector ..................................................................................................................................... 18

Frequency Synthesis ..................................................................................................................................... 18

3.3.1. Reference Oscillator.................................................................................................................................. 18

3.3.2. CLKOUT Output ........................................................................................................................................19

3.3.3. PLL Architecture........................................................................................................................................ 19

3.3.4. Lock Time ..................................................................................................................................................20

3.3.5. Lock Detect Indicator................................................................................................................................. 20

3.4.

Transmitter Description ..................................................................................................................................21

3.4.1. Architecture Description ............................................................................................................................ 21

3.4.2. Bit Rate Setting ......................................................................................................................................... 21

3.4.3. FSK Modulation......................................................................................................................................... 22

3.4.4. OOK Modulation........................................................................................................................................ 23

3.4.5. Modulation Shaping................................................................................................................................... 23

3.4.6. Power Amplifiers ....................................................................................................................................... 23

3.4.7. Over Current Protection ............................................................................................................................ 24

3.5.

Receiver Description ......................................................................................................................................25

3.5.1. Block Diagram ........................................................................................................................................... 25

3.5.2. LNA - Single to Differential Buffer ............................................................................................................. 25

3.5.3. Automatic Gain Control ............................................................................................................................. 26

3.5.4. Continuous-Time DAGC............................................................................................................................ 27

3.5.5. Quadrature Mixer - ADCs - Decimators ....................................................................................................28

3.5.6. Channel Filter ............................................................................................................................................ 28

3.5.7. DC Cancellation ........................................................................................................................................ 29

Rev. 7 - June 2013

Page 2

www.semtech.com

SX1231

WIRELESS & SENSING PRODUCTS

Table of contents

DATASHEET

Section

Page

3.5.8. Complex Filter - OOK ................................................................................................................................ 29

3.5.9. RSSI .......................................................................................................................................................... 29

3.5.10. Cordic ...................................................................................................................................................... 30

3.5.11. FSK Demodulator ....................................................................................................................................31

3.5.12. OOK Demodulator................................................................................................................................... 31

3.5.13. Bit Synchronizer ...................................................................................................................................... 33

3.5.14. Frequency Error Indicator........................................................................................................................ 33

3.5.15. Automatic Frequency Correction............................................................................................................. 34

3.5.16. Optimized Setup for Low Modulation Index Systems.............................................................................. 35

3.5.17. Temperature Sensor ...............................................................................................................................36

3.5.18. Timeout Function..................................................................................................................................... 36

Operating Modes ................................................................................................................................................... 37

4.1.

4.2.

Basic Modes .................................................................................................................................................. 37

Automatic Sequencer and Wake-Up Times................................................................................................... 37

4.2.1. Transmitter Startup Time ...........................................................................................................................38

4.2.2. Tx Start Procedure .................................................................................................................................... 38

4.2.3. Receiver Startup Time............................................................................................................................... 38

4.2.4. Rx Start Procedure.................................................................................................................................... 40

4.2.5. Optimized Frequency Hopping Sequences............................................................................................... 40

4.3.

Listen Mode ...................................................................................................................................................41

4.3.1. Timings...................................................................................................................................................... 41

4.3.2. Criteria....................................................................................................................................................... 42

4.3.3. End of Cycle Actions ................................................................................................................................. 42

4.3.4. Stopping Listen Mode................................................................................................................................ 43

4.3.5. RC Timer Accuracy ................................................................................................................................... 43

4.4.

5.1.

AutoModes .....................................................................................................................................................44

Overview ........................................................................................................................................................ 45

Data Processing .................................................................................................................................................... 45

5.1.1. Block Diagram ........................................................................................................................................... 45

5.1.2. Data Operation Modes .............................................................................................................................. 45

5.2.

Control Block Description............................................................................................................................... 46

5.2.1. SPI Interface.............................................................................................................................................. 46

5.2.2. FIFO .......................................................................................................................................................... 47

5.2.3. Sync Word Recognition............................................................................................................................. 48

5.2.4. Packet Handler.......................................................................................................................................... 49

5.2.5. Control....................................................................................................................................................... 49

5.3.

Digital IO Pins Mapping ................................................................................................................................. 49

5.3.1. DIO Pins Mapping in Continuous Mode .................................................................................................... 50

5.3.2. DIO Pins Mapping in Packet Mode ........................................................................................................... 50

Rev. 7 - June 2013

Page 3

www.semtech.com

SX1231

WIRELESS & SENSING PRODUCTS

Table of contents

DATASHEET

Section

5.4.

Page

Continuous Mode ...........................................................................................................................................51

5.4.1. General Description................................................................................................................................... 51

5.4.2. Tx Processing............................................................................................................................................ 51

5.4.3. Rx Processing ........................................................................................................................................... 52

5.5.

Packet Mode .................................................................................................................................................. 52

5.5.1. General Description................................................................................................................................... 52

5.5.2. Packet Format ........................................................................................................................................... 53

5.5.3. Tx Processing (without AES)..................................................................................................................... 55

5.5.4. Rx Processing (without AES) .................................................................................................................... 56

5.5.5. AES ........................................................................................................................................................... 56

5.5.6. Handling Large Packets ............................................................................................................................ 58

5.5.7. Packet Filtering.......................................................................................................................................... 58

5.5.8. DC-Free Data Mechanisms....................................................................................................................... 60

Configuration and Status Registers ....................................................................................................................... 62

6.1.

6.2.

6.3.

6.4.

6.5.

6.6.

6.7.

6.8.

7.1.

7.2.

General Description ....................................................................................................................................... 62

Common Configuration Registers ..................................................................................................................65

Transmitter Registers .....................................................................................................................................68

Receiver Registers .........................................................................................................................................69

IRQ and Pin Mapping Registers ....................................................................................................................71

Packet Engine Registers ................................................................................................................................73

Temperature Sensor Registers...................................................................................................................... 76

Test Registers................................................................................................................................................ 76

Crystal Resonator Specification..................................................................................................................... 77

Reset of the Chip ........................................................................................................................................... 77

Application Information .......................................................................................................................................... 77

7.2.1. POR........................................................................................................................................................... 77

7.2.2. Manual Reset ............................................................................................................................................78

7.3.

8.1.

8.2.

8.3.

8.4.

9.1.

9.2.

Reference Design .......................................................................................................................................... 78

QFN 24 Encapsulation................................................................................................................................... 81

TSSOP 28 Encapsulation ..............................................................................................................................82

Thermal Impedance ....................................................................................................................................... 82

Tape & Reel Specification.............................................................................................................................. 83

RC Oscillator Calibration................................................................................................................................ 84

Listen Mode ...................................................................................................................................................85

Packaging Information ........................................................................................................................................... 81

Chip Revisions....................................................................................................................................................... 84

9.2.1. Resolutions................................................................................................................................................ 85

9.2.2. Exiting Listen Mode ................................................................................................................................... 85

9.3.

OOK Floor Threshold Default Setting ............................................................................................................ 85

Page 4

www.semtech.com

Rev. 7 - June 2013

SX1231IMLTRT相似产品对比

	SX1231IMLTRT	SX1231ITSTRT
描述	Tactile Switches Top Actuated w/o boss w/o ground	RF Transceiver LOW-POWER INTG UHF TRANSCEIVER

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器件捷径: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

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