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Spartan and Spartan-XL FPGA
Families Data Sheet
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DS060 (v2.0) March 1, 2013
Product Specification
•
System level features
- Available in both 5V and 3.3V versions
- On-chip SelectRAM™ memory
- Fully PCI compliant
- Full readback capability for program verification
and internal node observability
- Dedicated high-speed carry logic
- Internal 3-state bus capability
- Eight global low-skew clock or signal networks
- IEEE 1149.1-compatible Boundary Scan logic
- Low cost plastic packages available in all densities
- Footprint compatibility in common packages
Fully supported by powerful Xilinx ISE
®
Classics
development system
- Fully automatic mapping, placement and routing
Introduction
The Spartan
®
and the Spartan-XL FPGA families are a
high-volume production FPGA solution that delivers all the
key requirements for ASIC replacement up to 40,000 gates.
These requirements include high performance, on-chip
RAM, core solutions and prices that, in high volume,
approach and in many cases are equivalent to mask pro-
grammed ASIC devices.
By streamlining the Spartan series feature set, leveraging
advanced process technologies and focusing on total cost
management, the Spartan series delivers the key features
required by ASIC and other high-volume logic users while
avoiding the initial cost, long development cycles and inher-
ent risk of conventional ASICs. The Spartan and Spar-
tan-XL families in the Spartan series have ten members, as
shown in
Table 1.
•
Additional Spartan-XL Family Features
Spartan/Spartan-XL FPGA Features
Note: The Spartan series devices described in this data
sheet include the 5V Spartan family and the 3.3V
Spartan-XL family. See the separate data sheets for more
advanced members for the Spartan Series.
•
•
•
•
•
•
•
First ASIC replacement FPGA for high-volume
production with on-chip RAM
Density up to 1862 logic cells or 40,000 system gates
Streamlined feature set based on XC4000 architecture
System performance beyond 80 MHz
Broad set of AllianceCORE and LogiCORE™
predefined solutions available
Unlimited reprogrammability
Low cost
Max
System
Gates
5,000
10,000
20,000
30,000
40,000
•
•
•
•
•
•
•
•
•
•
•
•
•
3.3V supply for low power with 5V tolerant I/Os
Power down input
Higher performance
Faster carry logic
More flexible high-speed clock network
Latch capability in Configurable Logic Blocks
Input fast capture latch
Optional MUX or 2-input function generator on outputs
12 mA or 24 mA output drive
5V and 3.3V PCI compliant
Enhanced Boundary Scan
Express Mode configuration
Table 1:
Spartan and Spartan-XL Field Programmable Gate Arrays
Logic
Device
XCS05 and XCS05XL
XCS10 and XCS10XL
XCS20 and XCS20XL
XCS30 and XCS30XL
XCS40 and XCS40XL
Cells
238
466
950
1368
1862
Typical
Gate Range
(Logic and RAM)
(1)
2,000-5,000
3,000-10,000
7,000-20,000
10,000-30,000
13,000-40,000
CLB
Matrix
10 x 10
14 x 14
20 x 20
24 x 24
28 x 28
Total
CLBs
100
196
400
576
784
Max.
Total
No. of
Avail. Distributed
Flip-flops User I/O RAM Bits
360
616
1,120
1,536
2,016
77
112
160
192
205
(2)
3,200
6,272
12,800
18,432
25,088
Notes:
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
2. XCS40XL provided 224 max I/O in CS280 package discontinued by
PDN2004-01.
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Spartan and Spartan-XL FPGA Families Data Sheet
R
General Overview
Spartan series FPGAs are implemented with a regular, flex-
ible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources (routing channels), and sur-
rounded by a perimeter of programmable Input/Output
Blocks (IOBs), as seen in
Figure 1.
They have generous
routing resources to accommodate the most complex inter-
connect patterns.
The devices are customized by loading configuration data
into internal static memory cells. Re-programming is possi-
ble an unlimited number of times. The values stored in these
memory cells determine the logic functions and intercon-
nections implemented in the FPGA. The FPGA can either
actively read its configuration data from an external serial
PROM (Master Serial mode), or the configuration data can
be written into the FPGA from an external device (Slave
Serial mode).
Spartan series FPGAs can be used where hardware must
be adapted to different user applications. FPGAs are ideal
for shortening design and development cycles, and also
offer a cost-effective solution for production rates well
beyond 50,000 systems per month.
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
CLB
IOB
CLB
CLB
CLB
IOB
B-
SCAN
OSC
IOB
IOB
IOB
CLB
IOB
Routing Channels
IOB
CLB
IOB
CLB
CLB
CLB
CLB
CLB
CLB
IOB
IOB
IOB
IOB
IOB
CLB
IOB
CLB
CLB
CLB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
RDBK
START
-UP
VersaRing Routing Channels
DS060_01_081100
Figure 1:
Basic FPGA Block Diagram
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DS060 (v2.0) March 1, 2013
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Spartan and Spartan-XL FPGA Families Data Sheet
Spartan and Spartan-XL devices provide system clock
rates exceeding 80 MHz and internal performance in
excess of 150 MHz. In addition to the conventional benefit
of high volume programmable logic solutions, Spartan
series FPGAs also offer on-chip edge-triggered single-port
and dual-port RAM, clock enables on all flip-flops, fast carry
logic, and many other features.
The Spartan/XL families leverage the highly successful
XC4000 architecture with many of that family’s features and
benefits. Technology advancements have been derived
from the XC4000XLA process developments.
Configurable Logic Blocks (CLBs)
The CLBs are used to implement most of the logic in an
FPGA. The principal CLB elements are shown in the simpli-
fied block diagram in
Figure 2.
There are three look-up
tables (LUT) which are used as logic function generators,
two flip-flops and two groups of signal steering multiplexers.
There are also some more advanced features provided by
the CLB which will be covered in the
Advanced Features
Description,
page 13.
Function Generators
Two 16 x 1 memory look-up tables (F-LUT and G-LUT) are
used to implement 4-input function generators, each offer-
ing unrestricted logic implementation of any Boolean func-
tion of up to four independent input signals (F1 to F4 or G1
to G4). Using memory look-up tables the propagation delay
is independent of the function implemented.
A third 3-input function generator (H-LUT) can implement
any Boolean function of its three inputs. Two of these inputs
are controlled by programmable multiplexers (see box "A" of
Figure 2).
These inputs can come from the F-LUT or G-LUT
outputs or from CLB inputs. The third input always comes
from a CLB input. The CLB can, therefore, implement cer-
tain functions of up to nine inputs, like parity checking. The
three LUTs in the CLB can also be combined to do any arbi-
trarily defined Boolean function of five inputs.
Logic Functional Description
The Spartan series uses a standard FPGA structure as
shown in
Figure 1, page 2.
The FPGA consists of an array
of configurable logic blocks (CLBs) placed in a matrix of
routing channels. The input and output of signals is
achieved through a set of input/output blocks (IOBs) forming
a ring around the CLBs and routing channels.
•
•
•
CLBs provide the functional elements for implementing
the user’s logic.
IOBs provide the interface between the package pins
and internal signal lines.
Routing channels provide paths to interconnect the
inputs and outputs of the CLBs and IOBs.
The functionality of each circuit block is customized during
configuration by programming internal static memory cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA.
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Spartan and Spartan-XL FPGA Families Data Sheet
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B
G-LUT
G4
G3
G2
G1
SR
H1
DIN
F4
F3
F2
F1
F4
Logic
F3 Function
of G
F2 F1-F4
F1
G4
Logic
G3 Function
of G
G1-G4
G2
G1
G
D
CK
EC
SR
Q
YQ
H-LUT
Logic
Function
H
H1 of
F-G-H1
F
SR
D
CK
EC
Q
XQ
Y
A
F-LUT
K
EC
Multiplexer Controlled
by Configuration Program
X
DS060_02_0506 01
Figure 2:
Spartan/XL Simplified CLB Logic Diagram (some features not shown)
A CLB can implement any of the following functions:
•
Any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables
Note:
When three separate functions are generated, one of
the function outputs must be captured in a flip-flop internal to
the CLB. Only two unregistered function generator outputs
are available from the CLB.
Flip-Flops
Each CLB contains two flip-flops that can be used to regis-
ter (store) the function generator outputs. The flip-flops and
function generators can also be used independently (see
Figure 2).
The CLB input DIN can be used as a direct input
to either of the two flip-flops. H1 can also drive either
flip-flop via the H-LUT with a slight additional delay.
The two flip-flops have common clock (CK), clock enable
(EC) and set/reset (SR) inputs. Internally both flip-flops are
also controlled by a global initialization signal (GSR) which
is described in detail in
Global Signals: GSR and GTS,
page 20.
•
•
•
Any single function of five variables
Any function of four variables together with some
functions of six variables
Some functions of up to nine variables.
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
Latches (Spartan-XL Family Only)
The Spartan-XL family CLB storage elements can also be
configured as latches. The two latches have common clock
(K) and clock enable (EC) inputs. Functionality of the stor-
age element is described in
Table 2.
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Spartan and Spartan-XL FPGA Families Data Sheet
Clock Input
Q
SR
SR
D
Q
Q
D
Q
Each flip-flop can be triggered on either the rising or falling
clock edge. The CLB clock line is shared by both flip-flops.
However, the clock is individually invertible for each flip-flop
(see CK path in
Figure 3).
Any inverter placed on the clock
line in the design is automatically absorbed into the CLB.
Clock Enable
The clock enable line (EC) is active High. The EC line is
shared by both flip-flops in a CLB. If either one is left discon-
nected, the clock enable for that flip-flop defaults to the
active state. EC is not invertible within the CLB. The clock
enable is synchronous to the clock and must satisfy the
setup and hold timing specified for the device.
Set/Reset
Don’t care
Rising edge (clock not inverted).
The set/reset line (SR) is an asynchronous active High con-
trol of the flip-flop. SR can be configured as either set or
reset at each flip-flop. This configuration option determines
the state in which each flip-flop becomes operational after
configuration. It also determines the effect of a GSR pulse
during normal operation, and the effect of a pulse on the SR
line of the CLB. The SR line is shared by both flip-flops. If
SR is not specified for a flip-flop the set/reset for that flip-flop
defaults to the inactive state. SR is not invertible within the
CLB.
Table 2:
CLB Storage Element Functionality
Mode
Power-Up or
GSR
Flip-Flop
Operation
CK
X
X
EC
X
X
1*
0
Latch
Operation
(Spartan-XL)
Both
Legend:
X
1
0
X
X
1*
1*
0
SR
X
1
0*
0*
0*
0*
0*
D
X
X
D
X
X
D
X
.
SR
0*
1*
Set or Reset value. Reset is default.
Input is Low or unconnected (default
value)
Input is High or unconnected (default
value)
CLB Signal Flow Control
SR
GND
GSR
SD
D
D
Q
Q
In addition to the H-LUT input control multiplexers (shown in
box "A" of
Figure 2, page 4)
there are signal flow control
multiplexers (shown in box "B" of
Figure 2)
which select the
signals which drive the flip-flop inputs and the combinatorial
CLB outputs (X and Y).
Each flip-flop input is driven from a 4:1 multiplexer which
selects among the three LUT outputs and DIN as the data
source.
Each combinatorial output is driven from a 2:1 multiplexer
which selects between two of the LUT outputs. The X output
can be driven from the F-LUT or H-LUT, the Y output from
G-LUT or H-LUT.
Control Signals
Multiplexer Controlled
by Configuration Program
DS060_03_041901
CK
RD
EC
Vcc
Figure 3:
CLB Flip-Flop Functional Block Diagram
There are four signal control multiplexers on the input of the
CLB. These multiplexers allow the internal CLB control sig-
nals (H1, DIN, SR, and EC in
Figure 2
and
Figure 4)
to be
driven from any of the four general control inputs (C1-C4 in
Figure 4)
into the CLB. Any of these inputs can drive any of
the four internal control signals.
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