VFxxx Controller Reference Manual
F-Series
Document Number: VYBRIDRM
Rev. 8, 11/2015
VFxxx Controller Reference Manual, Rev. 8, 11/2015
2
Freescale Semiconductor, Inc.
Contents
Section number
Title
Chapter 1
About This Document
1.1
Overview.........................................................................................................................................................................133
1.1.1
1.1.2
1.1.3
1.2
Purpose.............................................................................................................................................................133
Audience.......................................................................................................................................................... 133
Related Resources............................................................................................................................................ 133
Page
Conventions.................................................................................................................................................................... 134
1.2.1
1.2.2
1.2.3
Numbering systems..........................................................................................................................................134
Typographic notation....................................................................................................................................... 134
Special terms.................................................................................................................................................... 135
Chapter 2
Introduction
2.1
2.2
2.3
2.4
2.5
VFxxx Controller Platform............................................................................................................................................. 137
Feature Set...................................................................................................................................................................... 138
Detailed Block Diagram................................................................................................................................................. 139
Device Configuration......................................................................................................................................................140
Modules on the device.................................................................................................................................................... 142
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.5.8
2.5.9
Clocks...............................................................................................................................................................142
Platform Modules.............................................................................................................................................143
System Modules............................................................................................................................................... 147
Memories and Memory Interfaces................................................................................................................... 148
Audio modules................................................................................................................................................. 150
Timer modules................................................................................................................................................. 150
Communication interfaces............................................................................................................................... 152
Graphics Modules............................................................................................................................................ 153
Analog modules............................................................................................................................................... 155
VFxxx Controller Reference Manual, Rev. 8, 11/2015
Freescale Semiconductor, Inc.
3
Section number
Title
Chapter 3
Chip Configuration
Page
3.1
3.2
Introduction.....................................................................................................................................................................157
Core modules.................................................................................................................................................................. 157
3.2.1
3.2.2
3.2.3
3.2.4
Cortex-M4 Processor Core...............................................................................................................................157
Cortex-M4 Instruction Fetches on the System Bus......................................................................................... 159
Cortex-A5 Processor Core............................................................................................................................... 160
Interrupt Assignments...................................................................................................................................... 162
3.3
DMAMUX Request Sources.......................................................................................................................................... 169
3.3.1
DMAMUX Request Sources........................................................................................................................... 169
3.4
Wakeup Unit (WKPU)....................................................................................................................................................174
3.4.1
WKPU configuration....................................................................................................................................... 174
3.5
CMU Chip Signals..........................................................................................................................................................175
3.5.1
CMU Chip Signals........................................................................................................................................... 175
3.6
Cyclic Redundancy Check (CRC).................................................................................................................................. 176
3.6.1
CRC Reverse Logic Functions.........................................................................................................................176
3.7
3.8
External Watchdog Monitor........................................................................................................................................... 176
Timers............................................................................................................................................................................. 177
3.8.1
FlexTimer.........................................................................................................................................................177
3.8.1.1
3.8.1.2
3.8.1.3
3.8.1.4
3.8.1.5
3.8.1.6
3.8.2
Instantiation Information..............................................................................................................177
FTM Clock Input......................................................................................................................... 177
FTM Hardware Triggers.............................................................................................................. 177
FTM output triggers for other modules........................................................................................180
FTM Global Time Base............................................................................................................... 180
FTM Fault Detection Inputs.........................................................................................................181
Programmable Interrupt Timer(PIT)................................................................................................................181
3.8.2.1
3.8.2.2
PIT Instantiations......................................................................................................................... 181
PIT/DMA Periodic Trigger Assignments ................................................................................... 181
VFxxx Controller Reference Manual, Rev. 8, 11/2015
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Freescale Semiconductor, Inc.
Section number
3.8.3
Title
Page
Programmable Delay Block (PDB)..................................................................................................................182
3.8.3.1
PDB Instantiation......................................................................................................................... 182
3.8.3.1.1
3.8.3.1.2
3.8.3.2
3.8.3.3
3.8.3.4
3.8.3.5
PDB Output Triggers............................................................................................ 182
PDB Input Trigger Connections........................................................................... 182
PDB Module Interconnections.....................................................................................................183
DMA support on PDB .................................................................................................................183
PDB in Low-Power modes.......................................................................................................... 183
PDB implementation with ADC.................................................................................................. 184
3.8.4
Low-Power Timer (LPTMR)........................................................................................................................... 185
3.8.4.1
LPTMR prescaler/glitch filter clocking options.......................................................................... 185
3.9
External memory interfaces............................................................................................................................................ 185
3.9.1
Quad SPI.......................................................................................................................................................... 185
3.9.1.1
3.9.1.2
3.9.1.3
3.9.1.4
3.9.1.5
3.9.2
QuadSPI Instances....................................................................................................................... 185
QuadSPI Memory Interface......................................................................................................... 186
QuadSPI Buffer............................................................................................................................186
QuadSPI Clocking........................................................................................................................187
Booting from QuadSPI.................................................................................................................187
DRAM Controller............................................................................................................................................ 187
3.9.2.1
DDR maximum address space..................................................................................................... 187
3.9.3
Nand Flash Controller...................................................................................................................................... 188
3.9.3.1
Instantiation..................................................................................................................................188
3.9.4
FlexBus Controller........................................................................................................................................... 188
3.9.4.1
3.9.4.2
3.9.4.3
3.9.4.4
3.9.4.5
3.9.4.6
3.9.4.7
FlexBus signal multiplexing........................................................................................................ 188
VFxxx Controller restrictions...................................................................................................... 190
FlexBus Signal Multiplexing....................................................................................................... 190
FlexBus External Signal...............................................................................................................191
FlexBus Security.......................................................................................................................... 191
Instantiation Information..............................................................................................................191
FlexBus Chip Select Control Register (CSCR0) Reset Value..................................................... 193
VFxxx Controller Reference Manual, Rev. 8, 11/2015
Freescale Semiconductor, Inc.
5
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