OL2300
Fractional-N PLL based transmitter
Rev. 2 — 28 October 2010
Product data sheet
1. General description
The OL2300 is a UHF ASK/FSK fractional-N transmitter with a fully integrated fractional-N
Phase-Locked Loop (PLL) frequency synthesizer and a power amplifier to drive an
external antenna.
The OL2300 is especially designed for use in the Industrial Scientific Medical (ISM)
frequency bands (315/434/868/915 MHz). Fine-tuning of the reference oscillator by
means of fractional-N synthesis allows the compensation of manufacturing tolerances of
the crystal. The device also includes an adjustable output power capability.
The OL2300 can be used for both ASK and FSK modulation with chip rates up to
112 kcps. Due to the high-level of integration, few external components are needed to
construct a complete transmitter.
2. Features and benefits
Fully integrated fractional-N PLL frequency synthesizer
Integrated VCO without external components
Independent Power-down modes for oscillator and PLL
Operating frequency: 315/434/869/915 MHz ISM/SRD bands
OOK/ASK/FSK modulation
Software programmable output power
Software programmable modulation index for ASK
Software programmable frequency deviation for FSK
Software programmable multi channel capability
Software programmable crystal trimming capability
Low power operation
Very low external component count
Low pin-count
Very small package
NXP Semiconductors
OL2300
Fractional-N PLL based transmitter
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
OL2300NHN
−25 °C
to +85
°C
Name
HVQFN16
[1]
Description
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3
×
3
×
0.85 mm
Version
SOT758-1
Type number
[1]
When the exposed die attach pad is used, it must be connected to GND.
4. Functional diagram
OL2300
CONTROL LOGIC
TEST2
TEST1/SDO
EN
SCK
SDIO
CKOUT
SPI
BAUD-RATE
GENERATOR
FREQUENCY CONTROL
V
DD
VREG
V
DDA
V
DDD(PA)
V
SSA
V
SS
POWER SUPPLY
POWER DOWN LOGIC
PLL
/64...71
OSCILLATOR
XTAL2
OSC
XTAL1
f
REF
001aak379
TEST LOGIC
20
SPECIAL FUNCTION
REGISTER
POWER
AMPLIFIER
CONTROL
VOLTAGE REGULATOR
POWER AMPLIFIER
f
VCO
FBSL
PAOUT
XOSL
/2
PFD
CP
LPF
VCO
/2
V
SS(PA)
Fig 1.
Functional block diagram
OL2300
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 28 October 2010
2 of 46
NXP Semiconductors
OL2300
Fractional-N PLL based transmitter
5. Pinning information
5.1 Pinning
14 TEST1/SDO
15 CKOUT
terminal 1
index area
SCK
EN
XTAL2
XTAL1
1
2
13 TEST2
12 V
DDD(PA)
11 V
SS
10 PAOUT
9
8
16 SDIO
3
4
5
OL2300
GND
6
7
V
SS(PA)
VREG
V
DD
V
DDA
V
SSA
001aak380
Transparent top view
Fig 2.
Pin configuration SOT758-1 (HVQFN16)
5.2 Pin description
Table 2.
Symbol
SCK
EN
XTAL2
XTAL1
V
DD
VREG
V
DDA
V
SSA
V
SS(PA)
PAOUT
V
SS
V
DDD(PA)
TEST2
TEST1/SDO
CKOUT
SDIO
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
serial interface clock input
enable input
crystal oscillator 2
crystal oscillator 1
supply voltage
voltage regulator output
analog supply voltage
analog ground supply voltage
power amplifier ground supply voltage
power amplifier output
ground supply voltage
power amplifier digital supply voltage
test output 2
test output 1/serial data output
clock output
serial interface data input/output
OL2300
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 28 October 2010
3 of 46
NXP Semiconductors
OL2300
Fractional-N PLL based transmitter
6. Functional description
6.1 Functional blocks overview
6.1.1 Power management, voltage regulator
The supply voltage source is connected between pin V
DD
and the pins V
SS
, V
SSA
and
V
SS(PA)
.
An integrated low-dropout voltage regulator is used to supply the PLL and the PA-driver
with a reduced, regulated voltage. This helps keep the current consumption and the
supply voltage dependencies of the PLL as low as possible. The output of this regulator is
pin VREG which must be connected to an external blocking capacitor in order to
guarantee stability of the regulator. A recommended set-up is shown in
Figure 23.
Two different regulator modes are available. For a detailed description see
Section 6.4.6.
Pin V
DDA
is the positive supply voltage of the analog part of the PLL and pin V
DDD(PA)
is
the positive digital supply of the PLL prescaler and the PA-driver stage. Both pins should
be connected to pin VREG.
V
DD
0
PLLEN
REGULATOR
VREG
ENRAD
0
Ref
1
VDD
VCO
V
DDA
V
DDD(PA)
TXON
VREF
1
0
1
1
0
CASC
ENXR
TXON
0
AND
1
RF-POWER
AMPLIFIER
fracN-PLL
/64...71
BIAS
PAOUT
CRYSTAL
OSCILLATOR
PFD
CP
LPF
VCO
V
SS(PA)
V
SSA
V
SS
001aak381
Fig 3.
Power management
OL2300
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 28 October 2010
4 of 46
NXP Semiconductors
OL2300
Fractional-N PLL based transmitter
6.1.2 Interface and control logic
6.1.2.1
Configurable 3-wire or 4-wire interface
The OL2300 can be configured via a simple Serial Peripheral Interface (SPI). The
interface itself can be configured for 3-wire or 4-wire mode. The 4-wire mode uses pin
TEST1 as Serial Data Output SDO when the SDIO is used as input (see
Figure 4).
EN
pin must be set to enable communication via the 3 or 4-wire serial interface. If the EN
pin is kept low for at least 2
16
XTAL clock pulses, the transmitter device will be reset, the
bit-counter implemented inside the SPI counting the already transferred bits shall be set to
zero, SCK and SDIO are disabled and the device will enter the Power-down mode (also
the crystal oscillator is switched off). If the 4-wire interface has been used, a reset would
also deactivate the SDO pin (set to 3-state; ENSDO is not influenced).
3-wire interface
(transparent mode: baud-rate generated by
μC)
EN
MICROCONTROLLER
SCK
SDIO
OL2300
3-wire interface
(synchronized mode: baud-rate generated by Frantic)
EN
MICROCONTROLLER
SCK
SDIO
OL2300
CKOUT
4-wire interface
EN
SCK
SDI
SDO
CKOUT
MICROCONTROLLER
OL2300
001aak382
Fig 4.
Peripheral connection diagram
After a transmit command the EN pin has an additional function: At the falling edge of the
EN pin the level of the SDIO pin is latched and directly connected to the modulator input.
In this case it is possible to intercept the RF data transmission without deactivating the PA
and to loop the last transmitted bit while the SDIO interface is used for SFR configuration.
Note that EN must not be low for more than 2
16
XTAL clock pulses otherwise the device
will be reset.
SCK
pin is the clock input for the serial interface. Depending on the start-up condition of
SCK at the rising edge of EN (see
Section 6.7.9)
each rising/falling edge of SCK shifts
data into or gets data from the SPI register set. During RF data transmission the SCK is
don’t care (signal on SCK has no influence on interface).
OL2300
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 28 October 2010
5 of 46
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