MachXO3™ Family Data Sheet
Advance DS1047 Version 1.9, October 2017
MachXO3 Family Data Sheet
Introduction
October 2017
Advance Data Sheet DS1047
Features
Solutions
• Smallest footprint, lowest power, high data
throughput bridging solutions for mobile applica-
tions
• Optimized footprint, logic density, IO count, IO
performance devices for IO management and
logic applications
• High IO/logic, lowest cost/IO, high IO devices for
IO expansion applications
Flexible On-Chip Clocking
• Eight primary clocks
• Up to two edge clocks for high-speed I/O inter-
faces (top and bottom sides only)
• Up to two analog PLLs per device with frac-
tional-n frequency synthesis
— Wide input frequency range
(7 MHz to 400 MHz)
Flexible Architecture
• Logic Density ranging from 640 to 9.4K LUT4
• High IO to LUT ratio with up to 384 IO pins
Non-volatile, Multi-time Programmable
• Instant-on
— Powers up in microseconds
• Optional dual boot with external SPI memory
• Single-chip, secure solution
• Programmable through JTAG, SPI or I
2
C
• MachXO3L includes multi-time programmable
NVCM
• MachXO3LF infinitely reconfigurable Flash
— Supports background programming of non-
volatile memory
Advanced Packaging
• 0.4 mm pitch: 1K to 4K densities in very small
footprint WLCSP (2.5 mm x 2.5 mm to
3.8 mm x 3.8 mm) with 28 to 63 IOs
• 0.5 mm pitch: 640 to 9.4K LUT densities in
6 mm x 6 mm to 10 mm x 10 mm BGA packages
with up to 281 IOs
• 0.8 mm pitch: 1K to 9.4K densities with up to
384 IOs in BGA packages
TransFR Reconfiguration
• In-field logic update while IO holds the system
state
Pre-Engineered Source Synchronous I/O
•
•
•
•
DDR registers in I/O cells
Dedicated gearing logic
7:1 Gearing for Display I/Os
Generic DDR, DDRx2, DDRx4
Enhanced System Level Support
• On-chip hardened functions: SPI, I
2
C, timer/
counter
• On-chip oscillator with 5.5% accuracy
• Unique TraceID for system tracking
• Single power supply with extended operating
range
• IEEE Standard 1149.1 boundary scan
• IEEE 1532 compliant in-system programming
High Performance, Flexible I/O Buffer
• Programmable sysIO
TM
buffer supports wide
range of interfaces:
— LVCMOS 3.3/2.5/1.8/1.5/1.2
— LVTTL
— LVDS, Bus-LVDS, MLVDS, LVPECL
— MIPI D-PHY Emulated
— Schmitt trigger inputs, up to 0.5 V
hysteresis
• Ideal for IO bridging applications
• I/Os support hot socketing
• On-chip differential termination
• Programmable pull-up or pull-down mode
Applications
•
•
•
•
•
Consumer Electronics
Compute and Storage
Wireless Communications
Industrial Control Systems
Automotive System
Low Cost Migration Path
• Migration from the Flash based MachXO3LF to
the NVCM based MachXO3L
• Pin compatible and equivalent timing
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1047
Introduction_0.8
Introduction
MachXO3 Family Data Sheet
Table 1-1. MachXO3L/LF Family Selection Guide
Features
LUTs
Distributed RAM (kbits)
EBR SRAM (kbits)
UFM (kbits, MachXO3LF only)
Number of PLLs
Hardened
Functions:
IC
SPI
Timer/Counter
Oscillator
MIPI D-PHY Support
Multi Time Programmable
NVCM
Programmable Flash
Packages
36-ball WLCSP
(2.5 mm x 2.5 mm, 0.4 mm)
49-ball WLCSP
1
(3.2 mm x 3.2 mm, 0.4 mm)
81-ball WLCSP
1
(3.8 mm x 3.8 mm, 0.4 mm)
121-ball csfBGA
1
(6 mm x 6 mm, 0.5 mm)
256-ball csfBGA
1
(9 mm x 9 mm, 0.5 mm)
324-ball csfBGA
1
(10 mm x 10 mm, 0.5 mm)
256-ball caBGA
(14 mm x 14 mm, 0.8 mm)
324-ball caBGA
2
(15 mm x 15 mm, 0.8 mm)
400-ball caBGA
(17 mm x 17 mm, 0.8 mm)
484-ball caBGA
(19 mm x 19 mm, 0.8 mm)
1
2
MachXO3L-640/
MachXO3LF-640
MachXO3L-1300/
MachXO3LF-1300
MachXO3L-2100/
MachXO3LF-2100
MachXO3L-4300/
MachXO3LF-4300
MachXO3L-6900/
MachXO3LF-6900
MachXO3L-9400/
MachXO3LF-9400
640
5
64
64
1
2
1
1
1
Yes
MachXO3L-640
1300
10
64
64
1
2
1
1
1
Yes
MachXO3L-1300
2100
16
74
80
1
2
1
1
1
Yes
MachXO3L-2100
4300
34
92
96
2
2
1
1
1
Yes
MachXO3L-4300
6900
4
54
240
256
2
2
1
1
1
Yes
MachXO3L-6900
9400
4
73
432
448
2
2
1
1
1
Yes
MachXO3L-9400
MachXO3LF-640 MachXO3LF-1300 MachXO3LF-2100 MachXO3LF-4300 MachXO3LF-6900 MachXO3LF-9400
IO
28
38
63
100
100
206
100
206
268
206
2
206
2
279
100
206
268
206
2
279
335
2
206
281
206
2
279
335
2
335
3
384
3
206
3
206
1. Package is only available for E=1.2 V devices.
2. Package is only available for C=2.5 V/3.3 V devices in 6900 LUT and smaller densities. (Both C and E variants are available for 9400 LUT
devices).
3. Package is available for both E=1.2 V and C=2.5 V/3.3 V devices.
4. Refer to TN1289,
Power and Thermal Estimation and Management for MachXO3 Devices
for determination of safe ambient operating con-
ditions.
1-2
Introduction
MachXO3 Family Data Sheet
Introduction
MachXO3
TM
device family is an Ultra-Low Density family that supports the most advanced programmable bridging
and IO expansion. It has the breakthrough IO density and the lowest cost per IO. The device IO features have the
integrated support for latest industry standard IO.
The MachXO3L/LF family of low power, instant-on, non-volatile PLDs has five devices with densities ranging from
640 to 9400 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature
Embedded Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous
I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly
used functions such as SPI controller, I
2
C controller and timer/counter. MachXO3LF devices also support User
Flash Memory (UFM). These features allow these devices to be used in low cost, high volume consumer and sys-
tem applications.
The MachXO3L/LF devices are designed on a 65nm non-volatile low power process. The device architecture has
several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs
and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low
static power for all members of the family.
The MachXO3L/LF devices are available in two versions C and E with two speed grades: -5 and -6, with -6 being
the fastest. C devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3
V or 2.5 V. E devices only accept 1.2 V as the external VCC supply voltage. With the exception of power supply
voltage both C and E are functionally compatible with each other.
The MachXO3L/LF PLDs are available in a broad range of advanced halogen-free packages ranging from the
space saving 2.5 x 2.5 mm WLCSP to the 19 x 19 mm caBGA. MachXO3L/LF devices support density migration
within the same package. Table 1-1 shows the LUT densities, package and I/O options, along with other key
parameters.
The MachXO3L/LF devices offer enhanced I/O features such as drive strength control, slew rate control, PCI com-
patibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up,
pull-down and bus-keeper features are controllable on a “per-pin” basis.
A user-programmable internal oscillator is included in MachXO3L/LF devices. The clock output from this oscillator
may be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and
similar state machines.
The MachXO3L/LF devices also provide flexible, reliable and secure configuration from on-chip NVCM/Flash.
These devices can also configure themselves from external SPI Flash or be configured by an external master
through the JTAG test access port or through the I
2
C port. Additionally, MachXO3L/LF devices support dual-boot
capability (using external Flash memory) and remote field upgrade (TransFR) capability.
Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the
MachXO3L/LF family of devices. Popular logic synthesis tools provide synthesis library support for MachXO3L/LF.
Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place
and route the design in the MachXO3L/LF device. These tools extract the timing from the routing and back-anno-
tate it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of
reference designs licensed free of charge, optimized for the MachXO3L/LF PLD family. By using these configurable
soft core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design,
increasing their productivity.
1-3
MachXO3 Family Data Sheet
Architecture
October 2017
Advance Data Sheet DS1047
Architecture Overview
The MachXO3L/LF family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). All
logic density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM (EBRs).
Figure 2-1 and Figure 2-2 show the block diagrams of the various family members.
Figure 2-1. Top View of the MachXO3L/LF-1300 Device
Embedded Function
Block (EFB)
NVCM1/UFM
sysCLOCK PLL
sysMEM Embedded
Block RAM (EBR)
Configuration
NVCM0/Flash
Programmable Function Units
with Distributed RAM (PFUs)
PIOs Arranged into
sysIO Banks
Notes:
• MachXO3L/LF-640 is similar to MachXO3L/LF-1300. MachXO3L/LF-640 has a lower LUT count.
• MachXO3L devices have
NVCM,
MachXO3LF devices have Flash.
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1047
Introduction_0.9
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