PRELIMINARY
CY14V101QS
1-Mbit (128K × 8) Quad SPI nvSRAM
Features
■
■
Density
❐
1 Mbit (128K × 8)
Bandwidth
❐
108-MHz high-speed interface
❐
Read and write at 54 Mbps
Serial Peripheral Interface
❐
Clock polarity and phase modes 0 and 3
❐
Multi I/O option – Single SPI (SPI), Dual SPI (DPI), and Quad
SPI (QPI)
High reliability
❐
Infinite read, write, and RECALL cycles
❐
One million STORE cycles to nonvolatile elements (SONOS
FLASH Quantum trap)
❐
Data retention: 20 years at 85 °C
Read
❐
Commands: Normal, Fast, Dual I/O, and Quad I/O
❐
Modes: Burst Wrap, Continuous (XIP)
Write
❐
Commands: Normal, Fast, Dual I/O, and Quad I/O
❐
Modes: Burst Wrap, Continuous (XIP)
Data protection
❐
Hardware: Through Write Protect Pin (WP)
❐
Software: Through Write Disable instruction
❐
Block Protection: Status Register bits to control protection
Special instructions
❐
STORE/RECALL: Access data between SRAM and
Quantum Trap
❐
Serial Number: 8-byte customer selectable (OTP)
❐
Identification Number: 4-byte Manufacturer ID and Product
ID
Store from SRAM to nonvolatile SONOS FLASH Quantum Trap
❐
AutoStore: Initiated automatically at power-down with a small
capacitor (V
CAP
)
❐
Software: Using SPI instruction (STORE)
❐
Hardware: HSB pin
■
Recall from nonvolatile SONOS FLASH Quantum Trap to
SRAM
❐
Auto RECALL: Initiated automatically at power-up
❐
Software: Using SPI instruction (RECALL)
Low-power modes
❐
Sleep: Average current = 280 µA at 85 °C, 500 µA at 105 °C
❐
Hibernate: Average current = 8 µA at 85 °C, 10 µA at 105 °C
Operating supply voltages
❐
Core V
CC
: 2.7 V to 3.6 V
❐
I/O V
CCQ
: 1.71 V to 2.0 V
Temperature range
❐
Extended Industrial: –40 °C to 105 °C
❐
Industrial: –40 °C to 85 °C
Packages
❐
16-pin SOIC
❐
24-ball FBGA
■
■
■
■
■
■
■
Functional Overview
The Cypress CY14V101QS combines a 1-Mbit nvSRAM in a
monolithic integrated circuit with a QPI interface. The QPI allows
writing and reading the memory in either a single (one I/O
channel for one bit per clock cycle), dual (two I/O channels for
two bits per clock cycle), or quad (four I/O channels for four bits
per clock cycle) through the use of selected opcodes.
The memory is organized as 128K words of eight bits each
consisting of SRAM and nonvolatile SONOS FLASH Quantum
Trap cells. The SRAM provides infinite read and write cycles,
while the nonvolatile cells provide highly reliable nonvolatile
storage of data. Data transfers from SRAM to the nonvolatile
cells (STORE operation) take place automatically at
power-down. On power-up, data is restored to the SRAM from
the nonvolatile cells (RECALL operation). You can also initiate
the STORE and RECALL operations through SPI instruction.
■
■
■
■
Errata:
For information on silicon errata, see
“Errata”
on page 55. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 001-85257 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 24, 2015
PRELIMINARY
Contents
Pinout ................................................................................ 4
Pin Definitions ............................................................. 5
Device Operation .............................................................. 7
SRAM Write ................................................................. 7
SRAM Read ................................................................ 7
STORE Operation ....................................................... 7
AutoStore Operation .................................................... 7
Software STORE Operation ........................................ 8
Hardware STORE and HSB Pin Operation ................. 8
RECALL Operation ...................................................... 8
Hardware RECALL (Power-Up) .................................. 8
Software RECALL ....................................................... 8
Disabling and Enabling AutoStore ............................... 8
Quad Serial Peripheral Interface ..................................... 9
SPI Overview ............................................................... 9
Dual and Quad I/O Modes ......................................... 11
SPI Modes ................................................................. 11
SPI Operating Features .................................................. 12
Power-Up .................................................................. 12
Power-Down .............................................................. 12
Active Power Mode and Standby State ..................... 12
SPI Functional Description ............................................ 13
Status Register ............................................................... 15
Write Disable (WRDI) Instruction .............................. 18
Write Enable (WREN) Instruction .............................. 18
Enable DPI (DPIEN) Instruction ................................ 19
Enable QPI (QPIEN) Instruction ................................ 19
Enable SPI (SPIEN) Instruction ................................. 19
SPI Memory Read Instructions ...................................... 20
Read Instructions ...................................................... 20
Fast Read Instructions .............................................. 21
Write Instructions ....................................................... 24
System Resources Instructions .................................... 28
Software Reset (RESET) Instruction ......................... 28
Default Recovery Instruction ..................................... 29
Hibernate (HIBEN) Instruction ................................... 30
Sleep (SLEEP) Instruction ......................................... 31
Register Instructions ...................................................... 33
Read Status Register (RDSR) Instruction ................. 33
Write Status Register (WRSR) Instruction ................ 33
Read Configuration Register (RDCR) Instruction ...... 34
Write Configuration Register (WRCR) Instruction ..... 35
CY14V101QS
Identification Register (RDID) Instruction .................. 36
Identification Register (FAST_RDID) Instruction ....... 37
Serial Number Register Write (WRSN) Instruction .... 38
Serial Number Register Read (RDSN) Instruction .... 39
Fast Read Serial Number Register (FAST_RDSN)
Instruction .................................................................. 40
NV Specific Instructions ................................................ 41
Software Store (STORE) Instruction ......................... 41
Software Recall (RECALL) Instruction ...................... 41
Autostore Enable (ASEN) Instruction ........................ 42
Autostore Disable (ASDI) Instruction ......................... 42
HOLD Pin Operation ................................................. 43
Maximum Ratings ........................................................... 44
Operating Range ............................................................. 44
DC Specifications ........................................................... 44
Data Retention and Endurance ..................................... 46
Capacitance .................................................................... 46
Thermal Resistance ........................................................ 46
AC Test Loads and Waveforms ..................................... 46
AC Test Conditions ........................................................ 46
AC Switching Characteristics ....................................... 47
Switching Waveforms .................................................... 48
AutoStore or Power-Up RECALL .................................. 48
Switching Waveforms .................................................... 49
Software Controlled STORE and RECALL Cycles ...... 50
Switching Waveforms .................................................... 50
Hardware STORE Cycle ................................................. 51
Switching Waveforms .................................................... 51
Ordering Information ...................................................... 52
Ordering Code Definitions ......................................... 52
Package Diagrams .......................................................... 53
Acronyms ........................................................................ 54
Document Conventions ................................................. 54
Units of Measure ....................................................... 54
Errata ............................................................................... 55
Document History Page ................................................ 57
Sales, Solutions, and Legal Information ...................... 60
Worldwide Sales and Design Support ....................... 60
Products .................................................................... 60
PSoC
®
Solutions ....................................................... 60
Cypress Developer Community ................................. 60
Technical Support ..................................................... 60
Document Number: 001-85257 Rev. *H
Page 3 of 60
PRELIMINARY
CY14V101QS
Figure 3. 24-Ball FPGA Standard Pinout-Top View (Ball Side Down)
1
A
2
HSB
3
NC
4
NC
5
NC
B
NC
SCK
VSS
VCC
NC
C
NC
CS
NC
WP
(I/O2)
NC
D
VCAP
SO
(I/O1)
SI
(I/O0)
HOLD
(I/O3)
NC
E
NC
NC
NC
VCCQ
NC
Pin Definitions
Pin Description
I/O Type
Description
Input
HOLD (I/O3)
V
CCQ
V
CC
CS
SO (I/O1)
Input/Output
Power Supply
Power Supply
Input
Output
Input/Output
Input
WP (I/O2)
V
SS
Input/Output
Ground
HOLD pin. Suspends serial operation.
I/O3: When the part is in quad mode, the HOLD pin becomes I/O3 pin and acts as
input/output.
Power supply inputs for the I/Os of the device.
Power supply inputs to the core of the device.
Chip Select. Activates the device when pulled LOW. Driving this pin HIGH puts the
device in standby state.
Serial Output. Pin for output of data through SPI.
I/O1: When the part is in dual or quad mode, the SO pin becomes I/O1 pin and acts
as input/output.
Write Protect. Implements hardware write-protection in SPI.
I/O2: When the part is in quad mode, the WP pin becomes an I/O2 pin and acts as
input/output.
Ground power supply inputs to the core and I/Os of the device.
Hardware STORE Busy:
Output: Indicates the busy status of nvSRAM when LOW. After each Hardware and
Software STORE operation, HSB is driven HIGH for a short time (t
HHHD
) with standard
output HIGH current and then a weak internal pull-up resistor keeps this pin HIGH
(external pull-up resistor connection is optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
HSB
Input/Output
Document Number: 001-85257 Rev. *H
Page 5 of 60
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