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CD4029BDNSR

产品描述Counter Shift Registers PRESETTABLE UP-DOWN COUNTER, 100K
产品类别半导体    逻辑   
文件大小328KB,共11页
制造商Intersil ( Renesas )
官网地址http://www.intersil.com/cda/home/
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CD4029BDNSR概述

Counter Shift Registers PRESETTABLE UP-DOWN COUNTER, 100K

CD4029BDNSR规格参数

参数名称属性值
产品种类
Product Category
Counter Shift Registers
制造商
Manufacturer
Intersil ( Renesas )
RoHSDetails
系列
Packaging
Tube
工厂包装数量
Factory Pack Quantity
1

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DATASHEET
CD4029BMS
CMOS Presettable Up/Down Counter
FN3304
Rev 0.00
December 1992
Features
• High-Voltage Type (20V Rating)
• Medium Speed Operation: 8MHz (Typ.) at CL = 50pF
and VDD - VSS = 10V
• Multi-Package Parallel Clocking for Synchronous High
Speed Output Response or Ripple Clocking for Slow
Clock Input Rise and Fall Times
• “Preset Enable” and Individual “Jam” Inputs Provided
• Binary or Decade Up/Down Counting
• BCD Outputs in Decade Mode
• 100% Tested for Maximum Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1A at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and +25
o
C
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standards
No. 13B, “Standard Specifications for Description of
“B” Series CMOS Device’s
Description
CD4029BMS consists of a four-stage binary or BCD-decade up/
down counter with provisions for look-ahead carry in both count-
ing modes. The inputs consist of a single CLOCK, CARRY-IN
(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET
ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a
CARRY OUT signal are provided as outputs.
A high PRESET ENABLE signal allows information on the JAM
INPUTS to preset the counter to any state asynchronously with
the clock. A low on each JAM line, when the PRESET-ENABLE
signal is high, resets the counter to its zero count. The counter is
advanced one count at the positive transition of the clock when
the CARRY-IN and PRE-SET ENABLE signals are low.
Advancement is inhibited when the CARRY-IN or PRESET
ENABLE signals are high. The CARRY-OUT signal is normally
high and goes low when the counter reaches its maximum count
in the UP mode or the minimum count in the DOWN mode pro-
vided the CARRY-IN signal is low. The CARRY-IN signal in the
low state can thus be considered a CLOCK ENABLE. The
CARRY-IN terminal must be connected to VSS when not in use.
Binary counting is accomplished when the BINARY/DECADE
input is high; the counter counts in the decade mode when the
BINARY/DECADE input is low. The counter counts up when the
UP/DOWN input is high, and down when the UP/DOWN input is
low. Multiple packages can be connected in either a parallel-
clocking or a ripple-clocking arrangement as shown in Figure 17.
Parallel clocking provides synchronous control and hence faster
response from all counting outputs. Ripple-clocking allows for
longer clock input rise and fall times.
The CD4029BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
H4X
Frit Seal DIP
H1F
Ceramic Flatpack H6W
Applications
• Programmable Binary and Decade Counting/Fre-
quency Synthesizers-BCD Output
• Analog to Digital and Digital to Analog Conversion
• Up/Down Binary Counting
• Difference Counting
• Magnitude and Sign Generation
• Up/Down Decade Counting
Pinout
CD4029BMS
TOP VIEW
PRESET ENABLE 1
Q4 2
JAM 4 3
JAM 1 4
CARRY IN 5
Q1 6
CARRY OUT 7
VSS 8
16 VDD
15 CLOCK
14 Q3
13 JAM 3
12 JAM 2
11 Q2
10 UP/DOWN
9 BINARY/DECADE
Functional Diagram
PRESET
ENABLE
CARRY IN
1
(CLOCK
ENABLE) 5
BINARY/
DECADE
JAM INPUTS
1
2
3
4
VDD
16
6 Q1
11 Q2
Q3
BUFFERED
OUTPUTS
4 12 13 3
9
UP/DOWN 10
14
2
CLOCK
15
7
Q4
8
VSS
CARRY
OUT
FN3304 Rev 0.00
December 1992
Page 1 of 11

 
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