Datasheet
Serial EEPROM series Standard EEPROM
MicroWire BUS EEPROM (3-Wire)
BR93G76-3B
●General
Description
BR93G76-3B is serial EEPROM of serial 3-line Interface method.
They are 16bit organization and CS PIN is the third PIN in their PIN configuration.
●Features
■
3-line communications of chip select, serial clock,
serial data input / output (the case where input and
output are shared)
■
Operations available at high speed 3MHz clock
(4.5V ~ 5.5V)
■
High speed write available (write time 5ms max.）
■
Same package and pin configuration from 1Kbit to
16Kbit
■
1.7~5.5V single power source operation
■
Address auto increment function at read operation
■
Write mistake prevention function
» Write prohibition at power on
» Write prohibition by command code
» Write mistake prevention function at low voltage
■
Self-timed programming cycle
■
Program condition display by READY / BUSY
■
Compact package
SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/
TSSOP-B8J/DIP-T8/VSON008X2030
■
More than 40 years data retention
■
More than 1 million write cycles
■
Initial delivery state all addresses FFFFh
●Packages
W(Typ.) x D(Typ.)x H(Max.)
DIP-T8
9.30mm x 6.50mm x 7.10mm
TSSOP-B8
3.00mm x 6.40mm x 1.20mm
SOP8
5.00mm x 6.20mm x 1.71mm
TSSOP-B8J
3.00mm x 4.90mm x 1.10mm
SOP- J8
4.90mm x 6.00mm x 1.65mm
MSOP8
2.90mm x 4.00mm x 0.90mm
SSOP-B8
3.00mm x 6.40mm x 1.35mm
VSON008X2030
2.00mm x 3.00mm x 0.60mm
●
BR93G76-3B
Capacity
8Kbit
Bit format
512×16
Type
BR93G76-3B
Power source
voltage
1.7
~
5.5V
DIP-T8
*1
SOP8
SOP-J8
SSOP-B8
TSSOP-B8
TSSOP-B8J
MSOP8
VSON008
X2030
●
●
●
●
●
●
●
●
*1 DIP-T8 is not halogen free package
○Product
structure：Silicon monolithic integrated circuit
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© 2012 ROHM Co., Ltd. All rights reserved.
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○This
product is not designed protection against radioactive rays
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BR93G76-3B
●Absolute
Maximum Ratings
Parameter
Supply voltage
Symbol
VCC
Ratings
-0.3 to +6.5
800 (DIP-T8)
450 (SOP8)
450 (SOP-J8)
Permissible
dissipation
Pd
300 (SSOP-B8)
330 (TSSOP-B8)
310 (TSSOP-B8J)
310 (MSOP8)
300 (VSON008X2030)
Storage
temperature
Operating
temperature
Input voltage/
Output voltage
Junction
temperature
Tstg
Topr
‐
Tjmax
－65
to +150
－40
to +85
-0.3 to Vcc+1.0
150
℃
℃
V
℃
mW
Unit
V
Remarks
Datasheet
When using at Ta=25℃ or higher 8.0mW to be reduced per 1℃.
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.0mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.3mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.0mW to be reduced per 1℃.
The Max value of lnput voltage/Output voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value of Input
voltage/Output voltage is not under -0.8V.
Junction temperature at the storage condition
●Memory
cell characteristics (VCC=1.7½5.5V)
Limit
Parameter
Min.
Write cycles
*1
Data retention
*1
Unit
Typ.
-
-
Max.
-
-
Times
Years
Condition
1,000,000
40
Ta=25℃
Ta=25℃
○Shipment
data all address FFFFh
*1 Not 100% TESTED
●Recommended
Operation Ratings
Parameter
Supply voltage
Input voltage
Symbol
VCC
V
IN
Limits
1.7~5.5
V
Unit
0~VCC
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BR93G76-3B
●DC
characteristics
(Unless otherwise specified, VCC=1.7½5.5V, Ta=-40½+85℃)
Limits
Parameter
Symb
ol
Unit
Min.
-0.3
*1
0.7VCC
0
0
2.4
VCC-0.2
-1
-1
-
I
CC1
-
-
Supply current
I
CC2
-
-
I
CC3
-
Standby current
I
SB1
-
-
-
3.0
2.0
mA
µA
-
-
1.0
2.0
mA
mA
f
SK
=3MHz (READ)
VCC=2.5V, f
SK
=1MHz
t
E/W
=5ms (WRAL, ERAL)
VCC=5.5V ,f
SK
=3MHz
t
E/W
=5ms (WRAL, ERAL)
CS=0V
-
-
2.0
0.5
mA
mA
Typ.
-
-
-
-
-
-
-
-
-
Max.
0.3VCC
VCC+1.0
0.4
0.2
VCC
VCC
+1
+1
1.0
V
V
V
V
V
V
µA
µA
mA
1.7V≦VCC≦5.5V
1.7V≦VCC≦5.5V
Condition
Datasheet
Input low voltage
Input high voltage
Output low voltage 1
Output low voltage 2
Output high voltage 1
Output high voltage 2
Input leakage current1
Output leakage current
V
IL
V
IH
V
OL1
V
OL2
V
OH1
V
OH2
I
LI1
I
LO
I
OL
=2.1mA, 2.7V≦VCC≦5.5V
I
OL
=100μA
I
OH
=-0.4mA, 2.7V≦VCC≦5.5V
I
OH
=-100μA
V
IN
=0V~VCC(CS,SK,DI)
V
OUT
=0V~VCC, CS=0V
VCC=1.7V, f
SK
=1MHz, t
E/W
=5ms (WRITE)
VCC=5.5V ,f
SK
=3MHz, t
E/W
=5ms (WRITE)
f
SK
=1MHz (READ)
*1 When the pulse width is 50ns or less, the Min value of V
IL
is admissible to -0.8V.
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BR93G76-3B
●AC
characteristics
(Unless otherwise specified, VCC=1.7~2.5V, Ta=-40~+85℃)
Limits
Parameter
Symbol
Min.
Typ.
SK frequency
SK high time
SK low time
CS low time
CS setup time
DI setup time
CS hold time
DI hold time
Data “1” output delay
Data “0” output delay
Time from CS to output establishment
Time from CS to High-Z
Write cycle time
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
t
E/W
-
250
250
250
200
100
0
100
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Datasheet
Max.
1
-
-
-
-
-
-
-
400
400
400
200
5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
(Unless otherwise specified, VCC=2.5~4.5V, Ta=-40~+85℃)
Limits
Parameter
SK frequency
SK high time
SK low time
CS low time
CS setup time
DI setup time
CS hold time
DI hold time
Data “1” output delay
Data “0” output delay
Time from CS to output establishment
Time from CS to High-Z
Write cycle time
Symbol
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
t
E/W
Min.
-
230
200
200
50
100
0
100
-
-
-
-
-
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
2
-
-
-
-
-
-
-
200
200
150
100
5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
(Unless otherwise specified, VCC=4.5~5.5V, Ta=-40~+85℃)
Limits
Parameter
SK frequency
SK high time
SK low time
CS low time
CS setup time
DI setup time
CS hold time
DI hold time
Data “1” output delay
Data “0” output delay
Time from CS to output establishment
Time from CS to High-Z
Write cycle time
Symbol
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
t
E/W
Min.
-
100
100
200
50
50
0
50
-
-
-
-
-
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
3
-
-
-
-
-
-
-
200
200
150
100
5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
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BR93G76-3B
●Serial
input / output timing
Datasheet
CS
t
CSS
t
SKH
1/ f
SK
t
SKL
t
CSH
SK
t
DIS
t
D IH
DI
t
PD0
t
PD1
DO(READ)
t
SV
t
DF
DO(WRITE)
STATUS VALID
Figure 1. Sync data input / output timing
○Data
is taken by DI sync with the rise of SK.
○At
read operation, data is output from DO in sync with the rise of SK.
○The
STATUS signal at write (READY / BUSY) is output after t
CS
from the fall of CS after write command input, at the area
DO where CS is high, and valid until the next command start bit is input. And, while CS is low, DO becomes High-Z.
○After
completion of each mode execution, set CS low once for internal circuit reset, and execute the following operation
mode.
○1/f
SK
is the SK clock cycle, even if f
SK
is maximum, the SK clock cycle can’t be t
SKH
(Min.)+t
SKL
(Min.)
○For
“Write cycle time t
E/W
”, please see Figure 36,37,39,40.
○For
“CS low time t
CS
”, please see Figure 36,37,39,40.
●Block
diagram
CS
Command decode
Control
Power source voltage detection
SK
Clock generation
Write
prohibition
Address
buffer
9bit
High voltage occurrence
DI
Command
register
Address
decoder
9bit
8,192 bit
EEPROM
Data
DO
Dummy bit
register
16bit
R/W
amplifier
16bit
Figure 2. Block diagram
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