24LLC02
2K-bit Serial EEPROM for Low Power
OVERVIEW
The 24LLC02
serial EEPROM has a 2,048-bit capacity, supporting the standard
2
C™-bus serial interface.
I
It
is fabricated using Ceramate's most advanced CMOS technology. It has been developed for low power and low
voltage applications (1.8 V to 5.5 V). One of its major feature is a hardware-based write protection circuit for
the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP)
pin. Using one-page write mode, you can load up to 16 bytes of data into the EEPROM in a single write
operation. Another significant feature of the
24LLC02
is its support for fast mode and standard mode.
FEATURES
I C-Bus Interface
•
Two-wire serial interface
•
Automatic word address increment
EEPROM
•
•
•
•
•
•
2K-bit (2,048-bit/256-byte) storage area
16-byte page buffer
Hardware-based write protection for the entire
EEPROM (using the WP pin)
EEPROM programming voltage generated
on chip
1,000,000 erase/write cycles
100 years data retention
•
•
2
Operating Characteristics
•
•
Operating voltage
— 1.8 V to 5.5 V
Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200
µA
at 5.5 V
— Maximum stand-by current: < 5
µA
at 5.5 V
Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
•
Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 500 V (MM)
Packages
•
8-pin P-DIP , SOP , TSSOP
ORDERING INFORMATION
24 LLC
02
X
X
Operating Voltage
LLC:1.8~5.5V,CMOS
Type
02=2K
Temp. grade
Blank:-25℃~+70℃
Packing
Blank :Tube
A :Taping(SOP8)
T :Taping(TSSOP8)
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Email: server@ceramate.com.tw
Tel:886-3-3529445
Http: www.ceramate.com.tw
Page
1 of 19
Rev 1.2 May 6,2002
Fax:886-3-3521052
24LLC02
2K-bit Serial EEPROM for Low Power
SDA
Start/Stop
Logic
HV Generation
Timing Control
WP
Control Logic
EEPROM
Cell Array
SCL
Slave Address
Comparator
Word Address
Pointer
Row
decoder
256 x 8 bits
A0
A1
A2
Column Decoder
Data Register
D
OUT
and ACK
Figure 1-1.
24LLC02
Block Diagram
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Email: server@ceramate.com.tw
Tel:886-3-3529445
Http: www.ceramate.com.tw
Page
2 of 19
Rev 1.2 May 6,2002
Fax:886-3-3521052
24LLC02
2K-bit Serial EEPROM for Low Power
V
CC
WP
SCL
SDA
24LLC02
A0
A1
A2
V
SS
NOTE:
The
24LLC02
is available in 8-pin DIP, SOP,TSSOP package.
Figure 1-2. Pin Assignment Diagram
Table 1-1.
24LLC02
Pin Descriptions
Name
A0, A1, A2
Type
Input
Description
Input pins for device address selection. To configure a device address,
these pins should be connected to the V
CC
or V
SS
of the device.
These pins are internally pulled down to V
SS
.
Ground pin.
Bi-directional data pin for the I
2
C-bus serial data interface. Schmitt
trigger input and open-drain output. An external pull-up resistor must
be connected to V
CC.
Typical values for this pull-up resistor are 4.7 k
Ω
(100 kHz) and 1 k
Ω
(400 kHz).
Schmitt trigger input pin for serial clock input.
Input pin for hardware write protection control. If you tie this pin to V
CC,
the write function is disabled to protect previously written data in the
entire memory; if you tie it to V
SS
, the write function is enabled.
This pin is internally pulled down to V
SS
.
Single power supply.
Circuit
Type
1
V
SS
SDA
–
I/O
–
3
SCL
WP
Input
Input
2
1
V
CC
–
–
NOTE : See the following page for diagrams of pin circuit types 1, 2, and 3.
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Email: server@ceramate.com.tw
Tel:886-3-3529445
Http: www.ceramate.com.tw
Page
3 of 19
Rev 1.2 May 6,2002
Fax:886-3-3521052
24LLC02
2K-bit Serial EEPROM for Low Power
A0, A1,
A2, WP
SCL
Noise
Filter
Figure 1-3. Pin Circuit Type 1
Figure 1-4. Pin Circuit Type 2
SDA
Data Out
V
SS
Noise
Filter
Data In
Figure 1-5. Pin Circuit Type 3
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Email: server@ceramate.com.tw
Tel:886-3-3529445
Http: www.ceramate.com.tw
Page
4 of 19
Rev 1.2 May 6,2002
Fax:886-3-3521052
24LLC02
2K-bit Serial EEPROM for Low Power
FUNCTION DESCRIPTION
I C-BUS INTERFACE
The
24LLC02
supports the I C-bus serial interface data transmission protocol. The two-wire bus consists of a
serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to V
CC
by a
pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus
is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions
, controlling bus access. Using the A0, A1, and A2 input pins, up to eight
24LLC02
devices can be connected
to the same I
2
C-bus as slaves (see Figure 1-6). Both the master and slaves can operate as transmitter or receiver
, but the master device determines which bus operating mode would be active.
2
2
V
CC
V
CC
SDA
SCL
Slave 1
Bus Master
(Transmitter/
Receiver)
MCU
To V
CC
Slave 2
2 4 2 24LLC02
LLC
Tx/Rx
A0 A1 A2
Slave 3
24LLC02
Tx/Rx
A0 A1 A2
Slave 8
24LLC02
Tx/Rx
A0 A1 A2
24LLC02
Tx/Rx
A0 A1 A2
or V
SS
To V
CC
or V
SS
To V
CC
or V
SS
To V
CC
or V
SS
Figure 1-6. Typical Configuration (16 Kbits of Memory on the I
2
C-Bus)
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Email: server@ceramate.com.tw
Tel:886-3-3529445
Http: www.ceramate.com.tw
Page
5 of 19
Rev 1.2 May 6,2002
Fax:886-3-3521052
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