Preliminary Information
128K
X4283/85
CPU Supervisor with 128K EEPROM
DESCRIPTION
16K x 8 Bit
FEATURES
• Selectable watchdog timer
• Low V
CC
detection and reset assertion
—Four standard reset threshold voltages
—Adjust low V
CC
reset threshold voltage using
special programming sequence
—Reset signal valid to V
CC
= 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 128Kbits of EEPROM
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lock
™
protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8-lead SOIC
—8-lead TSSOP
BLOCK DIAGRAM
Watchdog Transition
Detector
WP
Data
Register
Command
Decode &
Control
Logic
V
CC
Threshold
Reset logic
Block Lock Control
Protect Logic
The X4283/85 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply Volt-
age Supervision, and Block Lock protect serial
EEPROM memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when V
CC
falls below the set minimum V
CC
trip point. RESET/RESET is asserted until V
CC
returns
to proper operating level and stabilizes. Four industry
Watchdog
Timer Reset
SDA
Status
Register
EEPROM Array
8Kb 4Kb 4Kb
RESET (X4283)
RESET (X4285)
SCL
S0
S1
Reset &
Watchdog
Timebase
V
CC
V
TRIP
+
-
Power on and
Low Voltage
Reset
Generation
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X4283/85 – Preliminary Information
standard Vtrip thresholds are available, however, Xicor’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock protection. The
array is internally organized as 64 bytes per page. The
device features an 2-wire interface and software proto-
col allowing operation on an 2-wire bus.
PIN CONFIGURATION
8-Pin JEDEC SOIC
S
0
S
1
RST/RST
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
8-Pin TSSOP
WP
V
CC
S
0
S
1
1
2
3
4
8
7
6
5
SCL
SDA
V
SS
RST/RST
PIN DESCRIPTION
Pin
(SOIC)
1
2
3
Pin
(TSSOP)
3
4
5
Name
S
0
S
1
RESET/
Device Select Input
Device Select Input
Function
RESET
Reset Output
. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V
CC
falls below the minimum V
CC
sense level. It will remain
active until V
CC
rises above the minimum V
CC
sense level for 250ms. RESET/
RESET goes active if the Watchdog Timer is enabled and SDA remains either
HIGH or LOW longer than the selectable Watchdog time out period. A falling edge
on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes
active on power up and remains active for 250ms after the power supply stabilizes.
Ground
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
Write Protect.
WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
Supply Voltage
4
5
6
7
V
SS
SDA
6
7
8
8
1
2
SCL
WP
V
CC
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X4283/85 – Preliminary Information
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X4283/85 activates a Power
On Reset Circuit that pulls the RESET/RESET pin
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When V
CC
exceeds the device V
TRIP
threshold value
for 200ms (nominal) the circuit releases RESET/
RESET allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X4283/85 monitors the V
CC
level
and asserts RESET/RESET if supply voltage falls
below a preset minimum V
TRIP
. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
CC
returns and exceeds
V
TRIP
for 200ms.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
V
CC
THRESHOLD RESET PROCEDURE
The X4283/85 is shipped with a standard V
CC
thresh-
old (V
TRIP
) voltage. This value will not change over nor-
mal operating and storage conditions. However, in
applications where the standard V
TRIP
is not exactly
right, or if higher precision is needed in the V
TRIP
value, the X4283/85 threshold may be adjusted. The
procedure is described below, and uses the application
of a nonvolatile control signal.
periodically, while SCL is HIGH (this is a start bit) prior
to the expiration of the watchdog time out period to pre-
vent a RESET/RESET signal. The state of two nonvola-
tile control bits in the Status Register determine the
watchdog timer period. The microprocessor can change
these watchdog bits, or they may be “locked” by tying
the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time-Out, any in-
progress communications are terminated. While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Non-volatile writes in-progress when RESET/RESET
goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
Figure 1. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
values WEL bit set)
V
P
= 12-15V
WP
0 1 2 3 4 5 6 7
SCL
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SDA
A0h
00h
01h
00h
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X4283/85 – Preliminary Information
Setting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a higher or
lower voltage value. It is necessary to reset the trip
point before setting the new value.
To set the new V
TRIP
voltage, start by setting the WEL
bit in the control register, then apply the desired V
TRIP
threshold voltage to the V
CC
pin and the programming
voltage, V
P
, to the WP pin and 2 byte address and 1
byte of “00” data. The stop bit following a valid write
operation initiates the V
TRIP
programming sequence.
Bring WP LOW to complete the operation.
Resetting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a “native”
voltage level. For example, if the current V
TRIP
is 4.4V
and the new V
TRIP
must be 4.0V, then the V
TRIP
must
be reset. When V
TRIP
is reset, the new V
TRIP
is some-
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the new V
TRIP
voltage start by setting the WEL
bit in the control register, apply V
CC
and the program-
ming voltage, V
P
, to the WP pin and 2 byte address and
1 byte of “00” data. The stop bit of a valid write opera-
tion initiates the V
TRIP
programming sequence. Bring
WP LOW to complete the operation.
Figure 2. Reset V
TRIP
Level Sequence (V
CC
> 3V. WP = 12-15V, WEL bit set)
WP
V
P
= 12-15V
0 1 2 3 4 5 6 7
SCL
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SDA
A0h
00h
03h
00h
Figure 3. Sample V
TRIP
Reset Circuit
V
P
SOIC
4.7K
RESET
V
TRIP
Adj.
1
2
3
4
X4283
8
7
6
5
Run
SCL
SDA
Adjust
µC
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X4283/85 – Preliminary Information
Figure 4. V
TRIP
Programming Sequence
V
TRIP
Programming
Execute
Reset V
TRIP
Sequence
Set V
CC
= V
CC
Applied =
Desired V
TRIP
New V
CC
Applied =
Old V
CC
Applied + Error
Execute
Set V
TRIP
Sequence
New V
CC
Applied =
Old V
CC
Applied - Error
Apply 5V to V
CC
Execute
Reset V
TRIP
Sequence
Decrement V
CC
(V
CC
= V
CC
- 50mV)
NO
RESET pin
goes active?
YES
Error
≤
–Emax
Error
≥
Emax
Measured V
TRIP
-
Desired V
TRIP
–Emax < Error < Emax
DONE
Emax = Maximum Allowed V
TRIP
Error
Control Register
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
The Control Register is accessed at address FFFFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Register" below.
The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, WD0, BP2, BP1, and BP0. The X4283/85 will not
acknowledge any data bytes written after the first byte
is entered.
REV 1.17 11/27/00
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Characteristics subject to change without notice.
5 of 22
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