NB3N853531E
3.3 V Xtal or
LVTTL/LVCMOS Input 2:1
MUX to 1:4 LVPECL Fanout
Buffer
Description
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MARKING
DIAGRAM
The NB3N853531E is a low skew 3.3 V supply 1:4 clock
distribution fanout buffer. An input MUX selects either a
Fundamental Parallel Mode Crystal or a LVCMOS/LVTTL Clock by
using the CLK_SEL pin (HIGH for Crystal, LOW for Clock) with
LVCMOS / LVTTL levels.
The single ended CLK input is translated to four LVPECL Outputs.
Using the crystal input, the NB3N853531E can be a Clock Generator.
A CLK_EN pin can enable or disable the outputs synchronously to
eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable
outputs, LOW to disable outputs).
Features
TSSOP−20
DT SUFFIX
CASE 948E
NB3N
531E
ALYWG
G
•
•
•
•
•
•
•
•
•
•
•
•
•
Four Differential 3.3 V LVPECL Outputs
Selectable Crystal or LVCMOS/LVTTL CLOCK Inputs
Up to 266 MHz Clock Operation
Output to Output Skew: 30 ps (Max)
Device to Device Skew 200 ps (Max)
Propagation Delay 1.8 ns (Max)
Operating Range: V
CC
= 3.3
±5%
V( 3.135 to 3.465 V)
Additive Phase Jitter, RMS: 0.053 ps (Typ)
Synchronous Clock Enable Control
Industrial Temp. Range (−40°C to 85°C)
Pb−Free TSSOP−20 Package
Ambient Operating Temperature Range
−40°C
to +85°C
These are Pb−Free Devices
CLK_EN
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 7 of this data sheet.
Pullup
D
Q
Q0
Q0
0
Q1
CLK
Pulldown
XTAL_IN
OSC
XTAL_OUT
1
Q1
Q2
Q2
Pulldown
Q3
Q3
CLK_SEL
Figure 1. Simplified Logic Diagram
©
Semiconductor Components Industries, LLC, 2012
March, 2012
−
Rev. 6
1
Publication Order Number:
NB3N853531E/D
NB3N853531E
V
EE
CLK_EN
CLK_SEL
CLK
nc
XTAL_IN
XTAL_OUT
nc
nc
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
Q0
V
CC
Q1
Q1
Q2
Q2
V
CC
Q3
Q3
Figure 2. Pinout Diagram (Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
3
4
5, 8, 9
6
7
10, 13, 18
11, 14, 16,
19
12, 15, 17,
20
Name
V
EE
CLK_EN
CLK_SEL
CLK
nc
XTAL_IN
XTAL_OUT
V
CC
Q[3:0]
Q[3:0]
LVPECL
LVPECL
Crystal
Crystal
LVCMOS /
LVTTL
LVCMOS /
LVTTL
LVCMOS /
LVTTL
Pullup
Pulldown
Pulldown
I/O
Open De-
fault
Description
Negative (Ground) Power Supply pin must be externally connected to
power supply to guarantee proper operation.
Synchronized Clock Enable when HIGH. When LOW, outputs are
disabled (Qx HIGH, Qx LOW)
Clock Input Select (HIGH selects crystal, LOW selects CLK input)
Clock Input. Float open when unused.
No Connect
Crystal Oscillator Input (used with pin 7). Float open when unused.
Crystal Oscillator Output (used with pin 6). Float open when unused.
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
Complement Differential Outputs (See AND8020 for termination)
True Differential Outputs (See AND8020 for termination)
Table 2. FUNCTIONS
Inputs
CLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Input Function
CLK input selected
Crystal Inputs Selected
CLK input selected
Crystal Inputs Selected
Output Function
Disabled
Disabled
Enabled
Enabled
Outputs
Qx
LOW
LOW
CLK0
CLK1
Qx
HIGH
HIGH
Invert of
CLK1
Invert of
CLK1
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3.
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2
NB3N853531E
CLK
CLK_EN
Disabled
Enabled
Q[0:3]
Q[0:3]
Figure 3. CLK_EN Timing Diagram
Table 3. ATTRIBUTES
(Note 2)
Characteristics
Internal Input Pullup Resistor
Internal Input Pulldown Resistor
C
in
Input Capacitance
ESD Protection
Human Body Model
Machine Model
Value
50 kW
50 kW
4 pF
> 2 kV
> 200 V
Level 1
UL 94 V−0 @ 0.125 in
28 to 34
333 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Flammability Rating
Oxygen Index
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
(Note 3)
Symbol
V
CC
V
in
I
out
T
A
T
stg
θ
JA
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range, Industrial
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
0 lfpm
Single−Layer
PCB (700 mm
2
,
2 oz)
Multi−Layer
PCB (700 mm
2
,
2 oz)
TSSOP−20
Continuous
Surge
Parameter
Condition 1
Condition 2
Rating
4.6
−0.5
v
V
I
v
VCC + 0.5
50
100
−40
to
v
+85
−65
to +150
128
Unit
V
V
mA
°C
°C
°C/W
200 lfpm
94
θ
JC
T
sol
Thermal Resistance (Junction−to−Case)
Wave Solder
(Note 4)
23 to 41
265
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power).
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3
NB3N853531E
Table 5. CRYSTAL CHARACTERISTICS AND CONNECTIONS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Min
Typ
Max
Unit
Fundamental Parallel
12
40
50
7
1
MHz
W
pF
mW
Table 6. DC CHARACTERISTICS
V
CC
= 3.3
±5%
V (3.135 to 3.465 V), V
EE
= 0 V, T
A
=
−40°C
to +85°C (Note 5)
Symbol
I
EE
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
VOUT
SWING
Power Supply Current
Input HIGH Voltage
Input LOW Voltage
Input High Current (V
CC
= 3.456 V)
Input LOW Current (V
CC
= 3.456 V)
Output HIGH Voltage
Output LOW Voltage
Output Voltage Swing (peak−to−peak)
CLK, CLK_SEL = 3.456 V
CLK_EN = 3.456 V
CLK, CLK_SEL = 3.456 V
CLK_EN = 3.456 V
−5
−150
V
CC
−
1.4
V
CC
−
2.0
0.6
V
CC
−
0.9
V
CC
−
1.7
1.0
2
−0.3
Characteristic
Min
Typ
Max
60
V
CC
+ 0.3
0.8
150
5
Unit
mA
V
V
mA
mA
V
V
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Outputs terminated 50
W
to V
CC
−
2.0 V, see Figure 4.
Table 7. AC CHARACTERISTICS
V
CC
= 3.3
±5%
V (3.135 to 3.465 V), V
EE
= 0 V, TA =
−40°C
to +85°C (Note 6)
Symbol
F
MAX
t
PD
tSKEW
DC
tSKEW
O−O
tSKEW
D−D
t
JIT
t
r
/t
f
Maximum Operating Frequency
Propagation Delay (Notes 7 and 9)
Duty Cycle Skew same path similar conditions at 50 MHz (Notes 7, 8 and 9)
Output to Output Skew Within A Device (Notes 7, 8 and 9)
Device to Device Skew similar path and conditions (Notes 7, 8 and 9)
Additive Phase Noise Jitter (RMS) @ 155.52 MHz (Integrated from 12 kHz to
20 MHz) See Figure 6. (Note 9)
Output rise and fall times (20% and 80% points) (Note 9)
225
0.053
600
Characteristic
Min
0
1.1
46
Typ
Max
266
1.8
54
30
200
Unit
MHz
ns
%
ps
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Outputs terminated 50
W
to V
CC
−
2.0 V, see Figure 4.
7. Measured under the same supply voltage, output loading, and input conditions.
8. Similar conditions.
9. Limits do not apply to overdriving XTAL_IN.
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NB3N853531E
2V
V
CC
Qx
Z
o
= 50
W
50
W
LVPECL
Qx
V
EE
Z
o
= 50
W
50
W
−1.3
±
0.165 V
Figure 4. Typical Test Setup and Termination for Evaluation. A split supply of V
CC
= 2.0 V and V
EE
=
−1.3
+0.165
V
allows a convenient direct connection termination into typical oscilloscope 50
W
to GND impedance modules.
For Application termination schemes see AND8020.
Input
t
PD
V
CC
/2
V
CC
/2
t
PD
80% 80%
Output
t
PW
Output
t
Period
20%
t
F
20%
t
R
tSKEW
DC
%
+
t
PW
t
Period
Duty Cycle Skew
−
t
SKEWDC
100
Propagation Delay t
PD
Input
Input
CLKx
tSKEW
0−0
CLKy
tSKEW
0−0
Part #1
Output
tSKEW
D−D
Part #2
Output
tSKEW
D−D
Output−to−Output Skew tSKEW
0−0
Device−to−Device Skew, tSKEW
D−D
Figure 5. AC Measurement Reference
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