MMBT6517L,
NSVMMBT6517L
High Voltage Transistor
NPN Silicon
Features
http://onsemi.com
COLLECTOR
3
1
BASE
2
EMITTER
•
NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS
Rating
Collector
−
Emitter Voltage
Collector
−
Base Voltage
Emitter
−
Base Voltage
Base Current
Collector Current
−
Continuous
Symbol
V
CEO
V
CBO
V
EBO
I
B
I
C
Value
350
350
5.0
25
100
Unit
V
V
V
mA
mA
3
1
2
THERMAL CHARACTERISTICS
Characteristic
Total Device Dissipation FR− 5 Board
(Note 1) T
A
= 25°C
Derate above 25°C
Thermal Resistance,
Junction−to−Ambient
Total Device Dissipation
Alumina Substrate, (Note 2) T
A
= 25°C
Derate above 25°C
Thermal Resistance,
Junction−to−Ambient
Junction and Storage Temperature
Symbol
P
D
Max
225
1.8
R
qJA
P
D
556
300
2.4
R
qJA
T
J
, T
stg
417
−55
to +150
Unit
mW
mW/°C
°C/W
mW
mW/°C
°C/W
°C
SOT−23 (TO−236AB)
CASE 318
STYLE 6
MARKING DIAGRAM
1Z M
G
G
1
1Z
= Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or overbar may
vary depending upon manufacturing location.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR− 5 = 1.0
0.75
0.062 in.
2. Alumina = 0.4
0.3
0.024 in. 99.5% alumina.
ORDERING INFORMATION
Device
MMBT6517LT1G
MMBT6517LT3G
Package
SOT−23
(Pb−Free)
SOT−23
(Pb−Free)
Shipping
†
3000 / Tape &
Reel
10,000 / Tape &
Reel
3,000 / Tape &
Reel
NSVMMBT6517LT1G SOT−23
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1
Publication Order Number:
MMBT6517LT1/D
©
Semiconductor Components Industries, LLC, 2013
October, 2013
−
Rev. 8
MMBT6517L, NSVMMBT6517L
200
V
CE
= 10 V
hFE , DC CURRENT GAIN
100
70
50
- 55°C
30
20
25°C
T
J
= 125°C
f T, CURRENT-GAIN — BANDWIDTH PRODUCT (MHz)
100
70
50
T
J
= 25°C
V
CE
= 20 V
f = 20 MHz
30
20
10
1.0
2.0
3.0
5.0 7.0 10
20 30
I
C
, COLLECTOR CURRENT (mA)
50 70 100
10
1.0
2.0
3.0
5.0 7.0 10
20 30
I
C
, COLLECTOR CURRENT (mA)
50 70
100
Figure 1. DC Current Gain
Figure 2. Current−Gain — Bandwidth Product
1.2
V, VOLTAGE (VOLTS)
1.0
0.8
0.6
0.4
0.2
0
1.0
T
J
= 25°C
R
θ
V, TEMPERATURE COEFFICIENTS (mV/
°
C)
1.4
2.5
2.0
1.5
1.0
0.5
0
R
qVC
for V
CE(sat)
- 55°C to 25°C
IC
+
10
IB
25°C to 125°C
V
BE(sat)
@ I
C
/I
B
= 10
V
BE(on)
@ V
CE
= 10 V
- 0.5
- 1.0
- 1.5
- 2.0
- 2.5
1.0
- 55°C to 125°C
R
qVB
for V
BE
V
CE(sat)
@ I
C
/I
B
= 10
V
CE(sat)
@ I
C
/I
B
= 5.0
2.0
3.0
5.0 7.0 10
20 30
I
C
, COLLECTOR CURRENT (mA)
50
70 100
2.0
Figure 3. “On” Voltages
3.0
5.0 7.0 10
20 30
I
C
, COLLECTOR CURRENT (mA)
50
70
100
Figure 4. Temperature Coefficients
C, CAPACITANCE (pF)
30
20
10
7.0
5.0
3.0
2.0
1.0
0.2
C
eb
I
C
, COLLECTOR CURRENT (mA)
100
70
50
1000
T
J
= 25°C
100
100 ms
10
1.0 s
1
10 ms
1 ms
C
cb
0.1
0.5
1.0 2.0
5.0
10
20
V
R
, REVERSE VOLTAGE (VOLTS)
50 100 200
1
10
100
V
CE
, COLLECTOR EMITTER VOLTAGE (V)
1000
Figure 5. Capacitance
Figure 6. Safe Operating Area
http://onsemi.com
3
MMBT6517L, NSVMMBT6517L
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AP
D
SEE VIEW C
3
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
DIM
A
A1
b
c
D
E
e
L
L1
H
E
q
MIN
0.89
0.01
0.37
0.09
2.80
1.20
1.78
0.10
0.35
2.10
0
°
MILLIMETERS
NOM
MAX
1.00
1.11
0.06
0.10
0.44
0.50
0.13
0.18
2.90
3.04
1.30
1.40
1.90
2.04
0.20
0.30
0.54
0.69
2.40
2.64
−−−
10
°
MIN
0.035
0.001
0.015
0.003
0.110
0.047
0.070
0.004
0.014
0.083
0
°
INCHES
NOM
0.040
0.002
0.018
0.005
0.114
0.051
0.075
0.008
0.021
0.094
−−−
MAX
0.044
0.004
0.020
0.007
0.120
0.055
0.081
0.012
0.029
0.104
10
°
E
1
2
HE
c
e
b
q
0.25
A
A1
L
L1
VIEW C
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
SOLDERING FOOTPRINT*
0.95
0.037
0.95
0.037
2.0
0.079
0.9
0.035
SCALE 10:1
0.8
0.031
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
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particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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5
MMBT6517LT1/D
嵌入式系统
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