NB4L6254
2.5V / 3.3V Differential
LVPECL 2x2 Clock Switch
and Low Skew Fanout
Buffer
Description
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MARKING DIAGRAMS*
The NB4L6254 is a differential 2x2 clock switch and drives
precisely aligned clock signals through its LVPECL fanout buffers. It
employs a fully differential architecture with bipolar technology,
offers superior digital signal characteristics, has very low clock output
skew and supports clock frequencies from DC up to 3.0 GHz.
The NB4L6254 is designed for the most demanding, skew critical
differential clock distribution systems. Typical applications for the
NB4L6254 are clock distribution, switching and data loopback
systems of high−performance computer, networking and
telecommunication systems, as well as on−board clocking of OC−3,
OC−12 and OC−48 communication systems. In addition, the
NB4L6254 can be configured as a single 1:6 or dual 1:3 LVPECL
fanout buffer.
The NB4L6254 can be operated from a single 3.3 V or 2.5 V power
supply.
Features
LQFP−32
FA SUFFIX
CASE 873A
1
NB4L
6254
AWLYYWWG
1
32
NB4L6254
AWLYYWWG
G
•
•
•
•
•
•
•
•
•
•
•
Maximum Clock Input Frequency, 3 GHz
Maximum Input Data Rate, 3 Gb/s
Differential LVPECL Inputs and Outputs
Low Output Skew: 50 ps Maximum Output−to−Output Skew
Synchronous Output Enable Eliminating Output Runt Pulse
Generation and Metastability
CLK0
CLK0
Operating Range: Single 3.3 V or 2.5 V Supply
V
CC
= 2.375 V to 3.465 V
LVCMOS Compatible Control Inputs
Packaged in LQFP−32
CLK1
Fully Differential Architecture
CLK1
−40°C
to 85°C Ambient Operating Temperature
These are Pb−Free Devices*
SEL0
SEL1
OEA
OEB
QFN32
MN SUFFIX
CASE 488AM
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
V
CC
Bank A
0
QA0
QA0
QA1
QA1
QA2
QA2
1
V
CC
Bank B
0
1
QB0
QB0
QB1
QB1
QB2
QB2
SYNC
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2009
March, 2009
−
Rev. 3
1
Publication Order Number:
NB4L6254/D
NB4L6254
QA0
QA0
V
CC
QA1
QA1
V
CC
QA2
QA2
32
V
CC
GND
SEL1
CLK1
CLK1
OEB
GND
V
CC
31
30
29
28
27
26
25
24
23
22
V
CC
GND
OEA
CLK0
CLK0
SEL0
GND
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NB4L6254
21
20
19
18
17
QB0
QB0
V
CC
QB1
QB1
V
CC
QB2
QB2
Figure 2. 32−Lead LQFP Pinout
(Top View)
QA0
QA0
V
CC
QA1
QA1
V
CC
QA2
QA2
Exposed Pad
(EP)
32
V
CC
GND
SEL1
CLK1
CLK1
OEB
GND
V
CC
31
30
29
28
27
26
25
24
23
22
V
CC
GND
OEA
CLK0
CLK0
SEL0
GND
V
CC
1
2
3
4
5
6
7
8
9
QB0
NB4L6254
21
20
19
18
17
10
QB0
11
V
CC
12
QB1
13
QB1
14
V
CC
15
QB2
16
QB2
Figure 3. 32−Lead QFN Pinout
(Top View)
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NB4L6254
Table 1. PIN DESCRIPTION
Pin Name
CLK0, CLK0
CLK1, CLK1
OEAb, OEB
SEL0, SEL1
QA[0−2], QA[0−2]
QB[0−2], QB[0−2]
GND
V
CC
EP
I/O
LVPECL Input
LVPECL Input
LVCMOS Input
LVCMOS Input
LVPECL Output
Power Supply
Power Supply
Description
Differential reference clock signal input 0.
Differential reference clock signal input 1.
Output Enable
Clock Switch Select
Differential LVPECL Clock Outputs, (banks A and B) Typically terminated with 50
W
resistor to V
CC
– 2.0 V.
Negative Supply Voltage
Positive supply voltage. All V
CC
pins must be connected to the positive power supply
for correct DC and AC operation.
The exposed pad (EP) on the QFN−32 package bottom is thermally connected to the
die for improved heat transfer out of the package. THe exposed pad must be attached
to a heat−sinking conduit. The pad is electrically connected to GND.
Table 2. FUNCTION TABLE
Control
OEA
Default
0
0
QA[0−2], QA[0−2] are active. Deassertion of
OEA can be asynchronous to the reference
clock without generation of output runt pulses
QB[0−2], QB[0−2] are active. Deassertion of
OEB can be asynchronous to the reference
clock without generation of output runt pulses
Refer to Table 3
1
QA[0−2] = L, QA[0−2] = H (outputs disabled). Assertion of
OE can be asynchronous to the reference clock without
generation of output runt pulses
QB[0−2] = L, QB[0−2] = H (outputs disabled). Assertion of
OE can be asynchronous to the reference clock without
generation of output runt pulses
Refer to Table 3
OEB
0
SEL0,
SEL1
00
Table 3. CLOCK SELECT CONTROL
SEL0
0
0
1
1
SEL1
0
1
0
1
CLK0 Routed To
QA[0:2] and QB[0:2]
−
QA[0:2]
QB[0:2]
−
QA[0:2] and QB[0:2]
QB[0:2]
QA[0:2]
CLK1 Routed to
Application Mode
1:6 Fanout of CLK0
1:6 Fanout of CLK1
Dual 1:3 Buffer
Dual 1:3 Buffer (Crossed)
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NB4L6254
Table 4. ATTRIBUTES
Characteristics
Internal Input Pullup Resistor
Internal Input Pulldown Resistor
ESD Protection
Latchup Immunity
Cin, inputs
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
LQFP−32
QFN32
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Value
37.5 kW
75 kW
> 2000 V
> 200 V
>200
mA
4.0 pF (TYP)
Level 2
Level 1
UL 94 V−0 @ 0.125 in
336
Table 5. MAXIMUM RATINGS
(Note 2)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
out
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
T
sol
V
TT
Parameter
Positive Power Supply
DC Input Voltage
DC Output Voltage
DC Input Current
LVPECL DC Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 3)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Output Termination Voltage
Pb−Free
0 lfpm
500 lfpm
2S2P (Note 3)
0 lfpm
500 lfpm
2S2P
LQFP−32
LQFP−32
LQFP−32
QFN−32
QFN−32
QFN−32
Continuous
Surge
LQFP−32
Condition
Condition
Rating
−0.3
v
V
CC
v
3.6
−0.3
v
V
IN
v
V
CC
+ 0.3
−0.3
v
V
OUT
v
V
CC
+ 0.3
$20
$50
100
−40
to +85
−65
to +150
80
55
12 to 17
31
27
12
265
V
CC
– 2.0, TYP
Unit
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. Maximum Ratings are those values beyond which device damage may occur.
3. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power); MIL−SPEC 883E Method 1012.1.
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NB4L6254
Table 6. DC CHARACTERISTICS
V
CC
= 2.375 V to 3.465 V, GND = 0 V, T
A
=
−40°C
to +85°C
Symbol
POWER SUPPLY CURRENT
I
GND
V
OH
Power Supply Current (Outputs Open)
60
85
mA
Characteristic
Min
Typ
Max
Unit
LVPECL CLOCK OUTPUTS
LVPECL Output HIGH Voltage (Notes 4, 5)
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
−
1145
2155
1355
V
CC
−
1945
1355
555
V
CC
−
1020
2280
1480
V
CC
−
1770
1530
730
V
CC
– 895
2405
1605
V
CC
−
1600
1700
900
mV
V
OL
LVPECL Output LOW Voltage (Notes 4, 5)
mV
CLOCK INPUTS
V
PP
V
CMR
V
IH
V
IL
I
IH
Dynamic Differential Input Voltage (Clock Inputs)
Differential Cross−point Voltage (Clock Inputs)
0.1
1.0
1.3
V
CC
−
0.3
V
V
LVCMOS CONTROL INPUTS
Output HIGH Voltage (LVTTL/LVCMOS)
Output LOW Voltage (LVTTL/LVCMOS)
Input Current V
IN
= V
CC
or V
IN
= GND
−100
2.0
0.8
+100
V
V
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVPECL Outputs loaded with 50
W
termination resistors to V
TT
= V
CC
– 2.0 V for proper operation.
5. LVPECL Output parameters vary 1:1 with V
CC
.
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