Package thermal resistances were obtained using the method described in JEDEC specifications. For detailed information on
package thermal considerations, refer to
www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3V to +5.5V, V
COM
= V
CC
, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Operating Voltage
Quiescent Current
Thermal Shutdown
Power-On Reset
Power-On Reset Hysteresis
DIGITAL INPUTS (SCLK, DIN,
CS,
LVL, A0, A1, A2,
RESET, SET)
Input Logic-High Voltage
Input Logic-Low Voltage
Input Logic Hysteresis
Input Leakage Currents
C
IN
Input Capacitance
DIGITAL OUTPUT (DOUT)
DOUT Low Voltage
DOUT High Voltage
V
OL
V
OH
I
SINK
= 6mA
I
SOURCE
= 0.5mA
V
CC
= 2.7V
V
CC
= 4.5V
R
ON
V
OUT
_
I
LEAK
V
FORW
V
CC
= 2.7V
V
CC
= 3.0V, I
OUT
_ = 70mA
V
OUT
_ = V
CC
, all outputs off
I
OUT
_ = 150mA (Note 3)
-1
V
CC
- 0.5
70
70
2
6
0.4
+1
1.5
0.4
V
V
V
IH
V
IL
V
HYST
I
LEAK
C
IN
Input voltages = 0V or 5.5V
-1.0
V
CC
= 3.3V
V
CC
= 5V
V
CC
= 3.3V
V
CC
= 5V
150
0.01
5
+1.0
2.0
2.4
0.6
0.8
V
V
mV
µA
pF
0.8
SYMBOL
V
CC
I
Q
I
OUT
_ = 0µA,
logic inputs = 0V or V
CC
V
CC
= 3.6V
V
CC
= 5.5V
CONDITIONS
MIN
2.3
15
20
160
1.5
140
2.2
TYP
MAX
5.5
50
70
UNITS
V
µA
°C
V
mV
RELAY OUTPUT DRIVERS (OUT1–OUT8)
OUT_ Drive Current
OUT_ On-Resistance
OUT_ Voltage
I
OUT
Off-Leakage Current
Kickback Diode Forward Voltage
mA
Ω
V
µA
V
2
Maxim Integrated
MAX4820/MAX4821
3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3V to +5.5V, V
COM
= V
CC
, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
SPI TIMING (MAX4820)
Turn-On Time (OUT_)
Turn-Off Time (OUT_)
SCLK Frequency
Cycle Time
CS
Fall to SCLK Rise Setup
CS
Rise to SCLK Hold
SCLK High Time
SCLK Low Time
Data Setup Time
Data Hold Time
SCLK Fall to DOUT Valid
Rise Time (DIN, SCLK,
CS, SET,
RESET)
Fall Time (DIN, SCLK,
CS,
RESET, SET)
RESET
Min Pulse Width
SET
Min Pulse Width
PARALLEL TIMING (MAX4821)
Turn-On Time
Turn-Off Time
LVL Setup Time
LVL Hold Time
Address to
CS
Setup Time
Address to
CS
Hold Time
Rise Time (A2, A1, A0, LVL)
Fall Time (A2, A1, A0, LVL)
RESET
Pulse Width
SET
Pulse Width
t
ON
t
OFF
t
LS
t
LH
t
AH
t
AS
t
SCR
t
SCF
t
RW
t
SW
20% of V
CC
to 70% of V
CC
, C
L
= 50pF
20% of V
CC
to 70% of V
CC
, C
L
= 50pF
70
70
From rising edge of
CS,
R
L
= 50Ω,
C
L
= 50pF
From rising edge of
CS,
R
L
= 50Ω,
C
L
= 50pF
100
0
100
0
2
2
1
1
µs
µs
ns
ns
ns
ns
µs
µs
ns
ns
t
ON
t
OFF
f
SCLK
t
CH
+ t
CL
t
CSS
t
CSH
t
CH
t
CL
t
DS
t
DH
t
DO
t
SCR
t
SCF
t
RW
t
SW
50% of SCLK to 10% of DOUT,
C
L
= 50pF
20% of V
CC
to 70% of V
CC
, C
L
= 50pF
20% of V
CC
to 70% of V
CC
, C
L
= 50pF
70
70
From rising edge of
CS,
R
L
= 50Ω,
C
L
= 50pF
From rising edge of
CS,
R
L
= 50Ω,
C
L
= 50pF
0
480
240
240
190
190
100
0
85
120
2
2
1.0
1.0
2.1
µs
µs
MHz
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Note 2:
Specifications at -40°C are guaranteed by design and not production tested.
Note 3:
After relay turn-off, inductive kickback may momentarily cause the voltage at OUT_ to exceed V
COM
. This is considered part
of normal operation and will not damage the device.
Maxim Integrated
3
MAX4820/MAX4821
+3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
Typical Operating Characteristics
(V
COM
= V
CC
, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX4820 toc01
SUPPLY CURRENT
vs. TEMPERATURE
V
CC
= 5V
20
SUPPLY CURRENT (μA)
V
CC
= 5.5V
MAX4820 toc02
SUPPLY CURRENT
vs. INPUT LOGIC VOLTAGE
900
800
SUPPLY CURRENT (μA)
700
600
500
400
300
200
100
V
CC
= 3.3V
V
CC
= 5V
ALL LOGIC INPUTS
CONNECTED
MAX4820 toc03
25
ALL LOGIC INPUTS = 0
20
SUPPLY CURRENT (μA)
25
1000
15
15
10
10
V
CC
= 3.3V
V
CC
= 2.3V
5
5
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
0
-40
-15
10
35
60
85
TEMPERATURE (°C)
0
0
1
2
3
4
5
INPUT LOGIC VOLTAGE (V)
ON-RESISTANCE
vs. SUPPLY VOLTAGE
MAX4820 toc04
ON-RESISTANCE
vs. TEMPERATURE
I
OUT_SINK
= 70mA
2.5
2.0
R
ON
(Ω)
1.5
1.0
V
CC
= 5.5V
0.5
0
V
CC
= 5V
V
CC
= 2.3V
V
CC
= 3.3V
MAX4820 toc05
POWER-ON RESET VOLTAGE
vs. TEMPERATURE
1.75
POWER-ON RESET VOLTAGE (V)
1.50
1.25
1.00
0.75
0.50
0.25
0
-40
-15
10
35
60
85
MAX4820 toc06
3.0
I
OUT_SINK
= 70mA
2.5
2.0
R
ON
(Ω)
1.5
1.0
0.5
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
3.0
2.00
5.5
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT OFF-LEAKAGE CURRENT
vs. SUPPLY VOLTAGE
MAX4820 toc07
OUTPUT OFF-LEAKAGE CURRENT
vs. TEMPERATURE
MAX4820 toc08
OUT_ TURN-ON/TURN-OFF DELAY TIMES
vs. SUPPLY VOLTAGE
R
L
= 50Ω
C
L
= 50pF
MAX4820 toc09
1.0
0.9
OUTPUT OFF-LEAKAGE (nA)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
2.00
1.75
OUTPUT OFF-LEAKAGE (nA)
1.50
1.25
1.00
0.75
0.50
0.25
0
V
CC
= 3.3V
-40
-15
10
35
60
V
CC
= 5V
V
CC
= 2.3V
V
CC
= 5.5V
80
70
t
ON
/t
OFF
DELAY TIME (ns)
60
50
t
OFF
40
30
20
t
ON
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
5.5
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
4
Maxim Integrated
MAX4820/MAX4821
3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
Typical Operating Characteristics (continued)
(V
COM
= V
CC
, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.)
INPUT LOGIC THRESHOLD
BACK EMF CLAMPING
vs. SUPPLY VOLTAGE
WITH STANDARD 3V RELAY
2.25
INPUT LOGIC THRESHOLD (V)
2.00
1.75
1.50
1.25
1.00
0.75
0.50
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
200μs/div
SUPPLY VOLTAGE (V)
0
OUT_ TURNS OFF
V
CC
= 3.3V
OUT_
1V/div
MAX4820 toc10
2.50
MAX4820 toc11
0
V
CS
5V/div
Pin Description
PIN
MAX4820
THIN
QFN
1
TSSOP
MAX4821
THIN
QFN
1
TSSOP
Reset Input. Drive
RESET
low to clear all latches and registers (all outputs
are turned off).
RESET
overrides all other inputs. If
RESET
and
SET
are pulled
low at the same time, then
RESET
takes precedence.
Chip-Select Input.
MAX4820:
Drive
CS
low to select the device. When
CS
is low, data at DIN is
clocked into the 8-bit shift register on SCLK’s rising edge. Drive
CS
from low
to high to latch the data to the registers and activate the appropriate relays.
MAX4821:
Drive
CS
low to select the device and set level on LVL. Drive
CS
from low to high to latch the address and level data to the output.
Serial-Data Input
Serial-Clock Input
Serial-Data Output. DOUT is the output of the 8-bit shift register. This output
can be used to daisy chain multiple MAX4820s. The data at DOUT appears
synchronous to SCLK’s falling edge.
No Connection
Ground
Open-Drain Output 8. Connect OUT8 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.
Open-Drain Output 7. Connect OUT7 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.
Power Ground. PGND is a return for the output sinks. Connect PGND pins
together and to GND.
Open-Drain Output 6. Connect OUT6 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.
LED 是light emitting diode (发光二极管)的缩写,是一种由半导体技术制成的电光源。LED的核心部分是由P型半导体和N型半导体组成的晶片,在P型半导体和N型半导体之间有一个过渡层,称为P2N结。在正向导通时,半导体中的多数载流子和少数载流子复合,释放出的能量以光子或部分以光子的形式发射出来,大量的光子形成光子流,即发光。P2N结加反向电压时,少数载流子难以注入,故不发...[详细]
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