MGA-14516
High Gain, High Linearity Active Bias Low Noise Amplifier
Data Sheet
Description
Avago Technologies’ MGA-14516 is a two stage, easy-to-
use GaAs MMIC Low Noise Amplifier (LNA) with active
bias. The LNA has low noise with good input return loss
and high linearity achieved through the use of Avago
Technologies’ proprietary 0.5um and 0.25um GaAs En-
hancement-mode pHEMT process. Both LNAs have an
extra feature inside that allows a designer to adjust supply
current. The first stage has an additional feature where the
gain can be adjusted externally without affecting noise
figure. Minimum matching needed for input, output and
the inter-stage between the two LNA.
It is designed for optimum use between 1.4GHz to 2.7GHz.
For optimum performance at lower frequency from
400MHz to 1.5GHz, the MGA-13516 is recommended.
Both MGA-13516 & MGA-14516 share the same package
and pinout.
Features
x
Low noise figure
x
High gain
x
Good IRL
x
High linearity performance
x
High reverse isolation
x
Externally adjustable supply current
x
Externally adjustable gain
x
GaAs E-pHEMT Technology
[1]
x
Low cost QFN package
x
Excellent uniformity in product specifications
Specifications
1.95GHz ; Q1 : 5V, 45mA (typ) Q2 : 5V, 110mA
x
31.7 dB Gain
x
0.68 dB Noise Figure
x
13 dB IRL
x
38 dBm Output IP3
x
23.5 dBm Output Power at 1dB gain compression
Pin Configuration and Package Marking
4.0 x 4.0 x 0.85 mm
3
16-lead QFN
Pin 13
Pin 12
Pin 11
Pin 10
Pin 9
Pin 8
Pin 7
Pin
6
Pin
5
Pin 14
Pin 15
Pin 16
Pin 1
Pin 2
Pin 3
Pin
4
14516
YYWW
XXXX
Applications
x
Low noise amplifier for cellular infrastructure including
GSM, CDMA, W-CDMA, TD-SCDMA and WiMAX.
x
Other very low noise applications.
Note:
1. Enhancement mode technology employs positive Vgs, thereby
eliminating the need of negative gate voltage associated with
conventional depletion mode devices.
TOP VIEW
BOTTOM VIEW
[16]
[15]
[14]
[13]
Pin
1
Description
Not Used
NC
RFin
RFgnd1
Vbias1
FB1
RFout1
RFin2
Pin
9
10
11
12
13
14
15
16
Description
Not Used
RFout
RFout
Not Used
Vg
RFgnd2
Vm
Vbias
[1]
[2]
Q2
Q1
5]
6]
7]
[3]
[4]
8]
[12]
[11]
[10]
[9]
2
3
4
5
6
7
8
Attention:
Observe
precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 40 V
ESD Human Body Model = 200 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Notes:
Package marking provides orientation and identification “14516” is the
Product Identification, “YYWW” is the Date Code, “XXXX” is the last 4
digits of the lot number.
Absolute Maximum Rating
[1]
Symbol
Vdd1
Vbias1
Vdd2
Vbias
Idd2
P
in,max
P
diss
T
j
T
STG
Parameter
Device Supply Voltage
Control Voltage
Device Voltage, RF output to ground
Control Voltage
Device Drain Current
CW RF Input Power (Vdd1 = 5.0V, Idd1=45mA)
Total Power Dissipation
[3]
Junction Temperature
Storage Temperature
Units
V
V
V
V
mA
dBm
W
°C
°C
Absolute Max.
5.5
3.5
5.5
5.5
150
20
1.30
150
-65 to 150
Thermal Resistance
[1-3]
(V
dd1
=V
dd2
=V
bias
=5V), θ
jc
= 36
o
C/W
Notes:
1. Operation of this device in excess of any of these limits may cause permanent damage.
2. Thermal resistance measured using Infra-Red Microscopy Technique.
3. Board temperature T
B
is 25
o
C. Derate 28mW/
o
C for T
B
>120
o
C.
Product Consistency Distribution Charts
[4]
T
A
= 25 °C, 1.95GHz, Vdd1=5V, Vdd2=5V, Vbias=5V, F
RF
=1.95GHz, unless stated otherwise.
LSL
USL
LSL
CPK = 2.67
USL
CPK = 3.08
34
36
38
40
42
44
46
48 50
Figure 1. Idd1 distribution ;
LSL
=
35mA, USL
= 52mA
LSL
CPK = 3.00
52
54
70
80
90
100
110
120
130
140
150
Figure
2.
Idd2 distribution ;
LSL
=
75mA, USL
= 140mA
USL
CPK = 3.72
USL
30.0
30.5
31.0
31.5
32.0
32.5
33.0
33.5
.60
.65
.70
.75
.80
.85
.90
.95
1.00
Figure
3.
Gain distribution ;
LSL
=
30.2dB, USL
=
33.3dB
Figure 4. NF distribution ;
USL
= 1dB
Notes:
4. Distribution data sample size is 500 samples taken from 3 different wafer lots. Future wafer allocated to this product may have nominal values
anywhere between the upper and lower limits. Circuit losses have not been de-embedded from actual measurements.
2
Demo Board Layout
Notes:
x
Recommended PCB material is 10 mils Rogers RO4350.
x
Suggested component values may vary according to layout and PCB
material.
x
L1 and C1 form the input matching network.
x
L4 and C7 form the output matching network.
x
L2, L3, C5 form the inter-stage matching network.
x
R2 and C4 form the network for externally gain adjustment feature.
(optional)
x
R4 and C18 form the network for externally gain adjustment feature.
(optional)
x
Cs, C6, C13 are RF bypass capacitor.
x
C16 mitigates the effect of external noise pickup on the Vbias line.
x
R1 is bias resistor for Q1.
Figure 5. Demo
Board Layout
Vbias=5V
C16
C6
Vdd2=5V
C11
L3
R4
C13
[16]
[15]
[14]
[13]
[1]
[2]
[12]
[11]
C18
L4
Q2
Q1
C1
[3]
L1
[4]
[10]
[9]
C7
[5]
[6]
[7]
Cs
[8]
L2
C10
C9
Vdd1=5V
R2
R1
Figure 6. Demo
Board
Schematic
3
C4
C5
Table1. 1.95 GHz Matching Components
Demo board (shown in Figure 5) component values used for demo board schematic in Figure 6. These component
values are used when measuring Electrical Specifications and plots of Figure 7 to Figure 17.
Part
Cs
C1
C5
C6
C7
C10
C13
C16
C18
L1
L2
L3
L4
R1
R4
Size
0402
0402
0402
0402
0402
0402
0402
0402
0402
0402
0402
0402
0402
0402
0402
Value
100pF
6.8pF
7.5pF
10pF
100pF
100pF
10pF
10pF
10pF
5.6nH
3.3nH
39nH
10nH
1.8kohm
220ohm
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Electrical Specifications
[1, 2]
T
A
= 25 °C, Vdd1=5V, Vdd2=5V, Vbias=5V, F
RF
=1.95GHz, unless stated otherwise.
Symbol
Idd1
Idd2
Ibias
Gain
NF
OIP3
OP1dB
IRL
ORL
S12
Parameter
and Test
Condition
Current at Q1
Current at Q2
Bias Current for Q2
Associated Gain
Noise Figure in 50Ω system
Output Third Order Intercept Point
(2-tone @ F
RF
+/- 1MHz, Pin = -25dBm)
Output Power at 1dB Gain Compression
Input Return Loss
Output Return Loss
Reverse Isolation
Units
mA
mA
mA
dB
dB
dBm
dBm
dB
dB
dB
Min.
35
75
Typ.
45
110
5
Max.
52
140
30.2
31.7
0.68
38
23.5
13
15
-50
33.3
1.0
Notes:
1. Measurements obtained using demo board described in Figure 5 with component list in Table 1. Input and Output trace loss is not de-embedded
from the measurement.
2. Guaranteed specifications are 100% tested in production test circuit.
4
MGA-14516 Typical Performance
T
A
= 25°C, Vdd1=5V, Vdd2=5V, Vbias=5V unless stated otherwise. Measured on demo board in Figure 5 with compo-
nents listed in Table 1.
60
50
40
Idd1 (mA)
30
20
40
10
0
-60
20
0
-40
-20
0
20
40
Temperature (°C)
60
80
100
-60
-40
-20
0
20
40
60
80
100
Temperature (°C)
140
120
100
Idd2 (mA)
Gain
(dB)
80
60
Figure
7.
Idd1 vs. Temperature
Figure
8.
Idd2 vs. Temperature
6
5
4
Ibias (mA)
3
2
1
0
-60
-40
-20
0
20
40
Temperature (°C)
60
80
100
36
34
32
30
28
26
24
1.65
1.75
1.85
1.95
Frequency (GHz)
2.05
2.15
-40°C
-30°C
25°C
85°C
Figure
9.
Ibias vs. Temperature
Figure 10. Gain vs. Frequency and Temperature
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
1.65
-40°C
-30°C
25°C
85°C
NF
(dB)
1.75
1.85
1.95
Frequency (GHz)
2.05
2.15
Figure 11. NF vs. Frequency and Temperature
5
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