CBTL06GP213
Second-generation high performance general purpose switch
Rev. 3.1 — 13 December 2016
Product data sheet
1. General description
The CBTL06GP213 is a six-channel (‘hex’) multiplexer for DisplayPort, HDMI and
PCI Express applications at Generation 2 (‘Gen2’) speeds. It provides four differential
channels capable of 1 : 2 switching or 2 : 1 multiplexing bidirectional, AC-coupled
PCI Express, DisplayPort signals, USB3 SuperSpeed or DC coupled TMDS signals, using
high-bandwidth pass-gate technology. It provides support for high common-mode/bias
voltage on the high-speed differential channels. Additionally, it provides for
switching/multiplexing of the Hot Plug Detect signal as well as the AUX or DDC (Display
Data Channel) signals, for a total of six channels on the display side. The AUX and DDC
channels provide a four-position multiplexer such that an additional level of multiplexing
can be accomplished when AUX and DDC I/Os are on separate pins of the display source
device.
The CBTL06GP213 is designed for Gen2 speeds, supporting 5.0 Gbit/s for PCI Express,
5.4 Gbit/s for DisplayPort or 6 Gbit/s for HDMI 2.0. It consumes 490
A
current (typical) in
operational mode and provides a shutdown function to support battery-powered
applications.
A typical application of CBTL06GP213 is on applications where one of two GPU display
sources must be selected to connect to a display sink device or connector. A controller
chip selects which path to use by setting a select signal HIGH or LOW. Due to the
non-directional nature of the signal paths (which use high-bandwidth pass gate
technology), the CBTL06GP213 can also be used in the reverse topology, for example, to
connect one display source device to one of two display sink devices or connectors.
2. Features and benefits
1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.2 - 5.4 Gbit/s) PCI Express
(v2.0 - 5.0 Gbit/s) signals, USB3 SuperSpeed or HDMI 2.0 (6 Gbit/s) TMDS signals
4 high-speed differential channels with 2 : 1 muxing/switching for DisplayPort or
PCI Express or HDMI signals
1 channel with 4 : 1 or 4 : 2 muxing/switching for AUX at 1 Mbit/s or DDC signals,
USB2 signals
1 channel with 2 : 1 muxing/switching for single-ended HPD signal
High-bandwidth analog pass-gate technology
Supports high-speed signal switching over a wide common-mode range and
differential swing
R
ON
on DP high-speed channels: 7
NXP Semiconductors
CBTL06GP213
Second-generation high performance general purpose switch
Low insertion loss:
0.9
dB at 100 MHz
1.1
dB at 1.35 GHz
1.3
dB at 2.7 GHz
3
dB bandwidth at 9.5 GHz
Low crosstalk:
32
dB at 2.7 GHz
Low off-state isolation:
23
dB at 2.7 GHz
Low return loss:
19
dB at 2.7 GHz
Very low intra-pair skew (5 ps typical)
Very low inter-pair skew (< 80 ps)
Switch/multiplexer position select CMOS input
Shutdown mode CMOS input
Supports backdrive protection
Single 3.3 V power supply
Operation current of 490
A
typical, shut-down current 10
A
maximum
ESD 2 kV HBM, 500 V CDM
Available in 5 mm
5 mm, 0.5 mm ball pitch TFBGA50 package
3. Applications
Motherboard applications requiring DisplayPort, HDMI, PCI Express, and USB
switching/multiplexing
Docking stations
Notebook computers
Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board
connectors
4. Ordering information
Table 1.
Ordering information
Topside Solder process
marking
Package
Name
Description
Version
plastic thin fine-pitch ball grid array package; SOT1345-1
50 balls; body 5
5
0.8 mm
[2]
Type number
CBTL06GP213EE
[1]
GP213
Pb-free (SnAgCu TFBGA50
solder compound)
[1]
[2]
Industrial temperature range.
Total height including solder balls after printed circuit board mounting = 1.15 mm.
For more information on product marking, refer to
www.nxp.com/products/related/package-markings.html.
CBTL06GP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
2 of 19
NXP Semiconductors
CBTL06GP213
Second-generation high performance general purpose switch
4.1 Ordering options
Table 2.
Ordering options
Orderable
part number
CBTL06GP213EEJ
Package
TFBGA50
Packing method
Reel 13” Q1/T1
*standard mark SMD
Minimum
Temperature
order quantity
3000
T
amb
=
40 C
to +105
C
Type number
CBTL06GP213EE
5. Functional diagram
VDD
DIN1_n+
DIN1_n−
DIN2_n+
DIN2_n−
4
4
4
DP
MUX
DOUT_n+
DOUT_n−
DAUX1+
DAUX1−
DAUX2+
DAUX2−
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_DAT2
AUX+ or SCL
AUX− or SDA
AUX/
DDC
MUX
AUX+
AUX−
DDC_CLK
DDC_DAT
HPD_1
HPD
MUX
HPD_2
HPDIN
GPU_SEL
DDC_AUX_SEL
XSD
GND
002aah658
Fig 1.
Functional diagram
CBTL06GP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
3 of 19
NXP Semiconductors
CBTL06GP213
Second-generation high performance general purpose switch
6. Pinning information
6.1 Pinning
ball A1
index area
CBTL06GP213EE
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
002aah659
Transparent top view
Fig 2.
Pin configuration for TFBGA50
1
A
B
C
D
E
F
G
H
J
AUX−
HPDIN
DOUT_1−
DOUT_2−
DOUT_3−
GPU_SEL
DOUT_0−
2
VDD
DOUT_0+
DDC_AUX
_SEL
DOUT_1+
DOUT_2+
DOUT_3+
GND
AUX+
HPD_1
3
4
DIN1_0−
5
DIN1_1−
DIN1_1+
6
DIN1_2−
DIN1_2+
7
8
DIN1_3+
9
DIN1_3−
DIN2_0−
GND
DIN1_0+
XSD
DIN2_0+
GND
DIN2_1+
DIN2_2+
DIN2_3+
GND
DIN2_1−
DIN2_2−
DIN2_3−
HPD_2
DDC_CLK
GND
VDD
DDC_CLK2
DDC_DAT2
DAUX2+
DAUX2−
GND
DDC_CLK1
DAUX1+
DAUX1−
002aah660
DDC_DAT DDC_DAT1
Transparent top view
Fig 3.
Ball mapping
CBTL06GP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
4 of 19
NXP Semiconductors
CBTL06GP213
Second-generation high performance general purpose switch
6.2 Pin description
Table 3.
Symbol
GPU_SEL
Pin description
Ball
A1
Type
3.3 V CMOS
single-ended input
Description
Selects between two multiplexer/switch paths. When HIGH,
path 2 left-side is connected to its corresponding right-side I/O.
When LOW, path 1 left-side is connected to its corresponding
right-side I/O. Refer to
Table 6
for switch connection details.
Tri-level select pin. Selects between DDC and AUX paths.
When HIGH, the AUX+ and AUX I/Os are connected to
appropriate DDC terminals. When LOW, the AUX+ and AUX
I/Os are connected to their appropriate AUX terminals. When
MID, AUX and DDC terminals are connected to the AUX+/
and DDC_CLK/DAT I/Os respectively. Refer to
Table 6
for
switch connection details.
Shutdown pin. Should be driven HIGH or connected to VDD for
normal operation. When LOW, all paths are switched off
(non-conducting high-impedance state) and supply current
consumption is minimized.
Four high-speed differential pairs for DisplayPort, PCI Express
or HDMI, USB3 signals, path 1, left-side.
DDC_AUX_SEL
C2
3.3 V CMOS
single-ended input
XSD
B7
3.3 V CMOS
single-ended input
DIN1_0+
DIN1_0
DIN1_1+
DIN1_1
DIN1_2+
DIN1_2
DIN1_3+
DIN1_3
DIN2_0+
DIN2_0
DIN2_1+
DIN2_1
DIN2_2+
DIN2_2
DIN2_3+
DIN2_3
DOUT_0+
DOUT_0
DOUT_1+
DOUT_1
DOUT_2+
DOUT_2
DOUT_3+
DOUT_3
DAUX1+
DAUX1
B4
A4
B5
A5
B6
A6
A8
A9
B8
B9
D8
D9
E8
E9
F8
F9
B2
B1
D2
D1
E2
E1
F2
F1
H9
J9
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
Four high-speed differential pairs for DisplayPort, PCI Express
or HDMI, USB3 signals, path 2, left-side.
Four high-speed differential pairs for DisplayPort, PCI Express
or HDMI, USB3 signals, right-side.
High-speed differential pair for AUX signals, path 1, left-side.
CBTL06GP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 13 December 2016
5 of 19
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