74HC4046A; 74HCT4046A
Phase-locked loop with VCO
Rev. 3 — 8 June 2016
Product data sheet
1. General description
The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in
compliance with JEDEC standard no 7A.
2. Features and benefits
Low power consumption
VCO-Inhibit control for ON/OFF keying and for low standby power consumption
Center frequency up to 17 MHz (typical) at V
CC
= 4.5 V
Choice of three phase comparators:
PC1: EXCLUSIVE-OR
PC2: Edge-triggered J-K flip-flop
PC3: Edge-triggered RS flip-flop
Excellent Voltage Controlled Oscillator (VCO) linearity
Low frequency drift with supply voltage and temperature variations
Operating power supply voltage range:
VCO section 3.0 V to 6.0 V
Digital section 2.0 V to 6.0 V
Zero voltage offset due to operational amplifier buffering
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Applications
FM modulation and demodulation
Frequency synthesis and multiplication
Frequency discrimination
Tone decoding
Data synchronization and conditioning
Voltage-to-frequency conversion
Motor-speed control
Nexperia
74HC4046A; 74HCT4046A
Phase-locked loop with VCO
7. Pinning information
7.1 Pinning
Fig 5.
Pin configuration
7.2 Pin description
Table 2.
Symbol
PCP_OUT
PC1_OUT
COMP_IN
VCO_OUT
INH
C1A
C1B
GND
VCO_IN
DEM_OUT
R1
R2
PC2_OUT
SIG_IN
PC3_OUT
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
phase comparator pulse output
phase comparator 1 output
comparator input
VCO output
inhibit input
capacitor C1 connection A
capacitor C1 connection B
ground (0 V)
VCO input
demodulator output
resistor R1 connection
resistor R2 connection
phase comparator 2 output
signal input
phase comparator 3 output
supply voltage
74HC_HCT4046A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 8 June 2016
4 of 50
Nexperia
74HC4046A; 74HCT4046A
Phase-locked loop with VCO
8. Functional description
The 74HC4046A; 74HCT4046A is a phase-locked-loop circuit that comprises a linear
voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and
PC3). It has a common signal input amplifier and a common comparator input (see
Figure 1).
The signal input can be directly coupled to a large voltage signal, or indirectly
coupled (with a series capacitor) to a small voltage signal. A self-bias input circuit keeps
small voltage signals within the linear region of the input amplifiers. With a passive
low-pass filter, the 74HC4046A; 74HCT4046A forms a second-order loop PLL. The
excellent VCO linearity is achieved by the use of linear op amp techniques.
8.1 VCO
The VCO requires one external capacitor C1 (between pins C1A and C1B) and one
external resistor R1 (between pins R1 and GND). Alternatively, it requires two external
resistors R1 and R2 (between pins R1 and GND, and R2 and GND). Resistor R1 and
capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to
have a frequency offset if necessary (see
Figure 4).
The high input impedance of the VCO simplifies the design of the low-pass filters by giving
the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is provided at pin DEM_OUT. In
contrast to conventional techniques, where the DEM_OUT voltage is one threshold
voltage lower than the VCO input voltage, the DEM_OUT voltage equals the VCO input. If
DEM_OUT is used, a series resistor (R
s
) should be connected from pin DEM_OUT to
GND; if unused, DEM_OUT should be left open. The VCO output (pin VCO_OUT) can be
connected directly to the comparator input (pin COMP_IN), or connected via a frequency
divider. When the VCO input DC level is held constant, the VCO output signal has a duty
cycle of 50 % (maximum expected deviation 1 %). A LOW-level at the inhibit input
(pin INH) enables the VCO and demodulator, while a HIGH-level turns both off to
minimize standby power consumption.
The only difference between the 74HC4046A and 74HCT4046A is the input level
specification of the INH input. This input disables the VCO section. The sections of the
comparator are identical, so that there is no difference in the SIG_IN or COMP_IN inputs
between the 74HC4046A and 74HCT4046A.
8.2 Phase comparators
The input signal can be coupled to the self-biasing amplifier at pin SIG_IN, when the
signal swing is between the standard HC family input logic levels. Capacitive coupling is
required for signals with smaller swings.
74HC_HCT4046A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 8 June 2016
5 of 50
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