®
VIPer50/SP
-
VIPer50A/ASP
SMPS PRIMARY I.C.
TYPE
VIPer50/SP
VIPer50A/ASP
s
ADJUSTABLE
V
DSS
620V
700V
I
n
1.5 A
1.5 A
R
DS(on)
5
Ω
5.7
Ω
10
SWITCHING FREQUENCY UP
TO 200 kHz
s
CURRENT MODE CONTROL
s
SOFT START AND SHUT DOWN CONTROL
s
AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
“BLUE ANGEL” NORM (<1W TOTAL POWER
CONSUMPTION)
s
INTERNALLY TRIMMED ZENER REFERENCE
s
UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
s
INTEGRATED START-UP SUPPLY
s
AVALANCHE RUGGED
s
OVERTEMPERATURE PROTECTION
s
LOW STAND-BY CURRENT
s
ADJUSTABLE CURRENT LIMITATION
PENTAWATT HV
1
PENTAWATT HV
(022Y)
PowerSO-10™
BLOCK DIAGRAM
O
bs
l
o
te
e
V
DD
ro
P
uc
d
UVLO
LOGIC
s)
t(
R/S
FF
S
so
b
-O
OSC
DESCRIPTION
VIPer50
™
/50A, made using VIPower M0
Technology, combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltage avalanche rugged Vertical
Power MOSFET (620V or 700V / 1.5A).
Typical applications cover off line power supplies
with a secondary power capability of 25W in wide
range condition and 50W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the possibility to operate in stand-by
mode without extra components.
P
te
le
od
r
s)
t(
uc
DRAIN
ON/OFF
OSCILLATOR
SECURITY
LATCH
Q
PWM
LATCH
S
R1 FF Q
R2 R3
OVERTEMP.
DETECTOR
0.5V
_
+ +
_
0.5 V
ERROR
_ AMPLIFIER
13 V
+
+
_
1.7
µ
s
DELAY
250 ns
BLANKING
2 V/A
CURRENT
AMPLIFIER
COMP
SOURCE
May 2003
FC00291
4.5 V
1/23
1
VIPer50/SP - VIPer50A/ASP
ABSOLUTE MAXIMUM RATING
Symbol
V
DS
I
D
V
DD
V
OSC
V
COMP
I
COMP
V
esd
I
D(AR)
P
tot
T
j
T
stg
Parameter
Continuous Drain-Source Voltage (T
j
=25 to 125°C)
for
VIPer50/SP
for
VIPer50A/ASP
Maximum Current
Supply Voltage
Voltage Range Input
Voltage Range Input
Maximum Continuous Current
Electrostatic Discharge (R =1.5kΩ; C=100pF)
Avalanche Drain-Source Current, Repetitive or Not Repetitive
(T
C
=100°C; Pulse width limited by T
j
max;
δ
< 1%)
for
VIPer50/SP
for
VIPer50A/ASP
Power Dissipation at T
c
=25ºC
Junction Operating Temperature
Storage Temperature
Value
-0.3 to 620
-0.3 to 700
Internally limited
0 to 15
0 to V
DD
0 to 5
±2
4000
1.5
1
60
Internally limited
-65 to 150
Unit
V
V
A
V
V
V
mA
V
A
THERMAL DATA
Symbol
R
thj-case
R
thj-amb.
Parameter
Thermal Resistance Junction-case
Thermal Resistance Ambient-case
Max
Max
PENTAWATT HV
1.9
60
(*) When mounted using the minimum recommended pad size on FR-4 board.
CONNECTION DIAGRAMS (Top View)
PENTAWATT HV
PENTAWATT HV (022Y)
CURRENT AND VOLTAGE CONVENTIONS
b
O
so
te
le
ro
P
V
DD
uc
d
s)
t(
so
b
-O
P
te
le
PowerSO-10™ (*)
1.9
50
od
r
s)
t(
uc
W
°C
°C
Unit
°C/W
°C/W
A
PowerSO-10™
I
DD
I
D
VDD
DRAIN
I
OSC
OSC
-
13V
+
COMP SOURCE
V
DS
I
COMP
V
OSC
V
COMP
FC00020
2/23
1
VIPer50/SP - VIPer50A/ASP
ORDERING NUMBERS
PENTAWATT HV
VIPer50
VIPer50A
PENTAWATT HV (022Y)
VIPer50 (022Y)
VIPer50A (022Y)
PowerSO-10™
VIPer50SP
VIPer50ASP
PINS FUNCTIONAL DESCRIPTION
DRAIN PIN:
Integrated Power MOSFET drain pin. It provides
internal bias current during start-up via an
integrated high voltage current source which is
switched off during normal operation. The device
is able to handle an unclamped current during its
normal operation, assuring self protection against
voltage surges, PCB stray inductance, and
allowing a snubberless operation for low output
power.
SOURCE Pin:
Power MOSFET source pin. Primary side circuit
common ground connection.
VDD Pin:
This pin provides two functions:
source, and can easily be connected to the
output of an optocoupler. Note that any
overvoltage due to regulation loop failure is still
detected by the error amplifier through the V
DD
voltage, which cannot overpass 13V. The
output voltage will be somewhat higher than the
nominal one, but still under control.
COMP PIN:
This pin provides two functions:
- It corresponds to the low voltage supply of the
control part of the circuit. If V
DD
goes below 8V,
the start-up current source is activated and the
output power MOSFET is switched off until the
V
DD
voltage reaches 11V. During this phase,
the internal current consumption is reduced,
the V
DD
pin sources a current of about 2mA
and the COMP pin is shorted to ground. After
that, the current source is shut down, and the
device tries to start up by switching again.
O
so
b
- This pin is also connected to the error amplifier,
in order to allow primary as well as secondary
regulation configurations. In case of primary
regulation, an internal 13V trimmed reference
voltage is used to maintain V
DD
at 13V. For
secondary regulation, a voltage between 8.5V
and 12.5V will be put on V
DD
pin by transformer
design, in order to stick the output of the
transconductance amplifier to the high state.
The COMP pin behaves as a constant current
te
le
ro
P
uc
d
s)
t(
so
b
-O
- It is the output of the error transconductance
amplifier, and allows for the connection of a
compensation network to provide the desired
transfer function of the regulation loop. Its
bandwidth can easily be adjusted to the
needed value with usual components value. As
stated
above,
secondary
regulation
configurations are also implemented through
the COMP pin.
P
te
le
od
r
s)
t(
uc
- When the COMP voltage goes below 0.5V, the
shut-down of the circuit occurs, with a zero
duty cycle for the power MOSFET. This feature
can be used to switch off the converter, and is
automatically activated by the regulation loop
(whatever is the configuration) to provide a
burst mode operation in case of negligible
output power or open load condition.
OSC PIN:
An R
t
-C
t
network must be connected on that pin to
define the switching frequency. Note that despite
the connection of R
t
to V
DD
, no significant
frequency change occurs for V
DD
varying from 8V
to 15V. It also provides a synchronization
capability, when connected to an external
frequency source.
3/23
1
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