144-Mbit QDR II SRAM Four-Word
Burst Architecture
144-Mbit QDR
®
II SRAM Four-Word Burst Architecture
CY7C1613KV18/CY7C1615KV18
®
Features
■
Configuration
CY7C1613KV18 – 8 M × 18
CY7C1615KV18 – 4 M × 36
Separate independent read and write data ports
❐
Supports concurrent transactions
333 MHz clock for high bandwidth
Four-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
Quad data rate (QDR
®
) II operates with 1.5-cycle read latency
when DOFF is asserted high
Operates similar to a QDR I device with one-cycle read latency
when DOFF is asserted low
Available in × 18, and × 36 configurations
Full data coherency, providing most current data
Core V
DD
= 1.8 V (±0.1 V); I/O V
DDQ
= 1.4 V to V
DD
❐
Supports both 1.5 V and 1.8 V I/O supply
Available in 165-ball fine-pitch ball grid array (FBGA) package
(15 × 17 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
Variable drive high-speed transceiver logic (HSTL) output
buffers
JTAG 1149.1 compatible test access port (TAP)
Phase Locked Loop (PLL) for accurate data placement
■
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■
Functional Description
The CY7C1613KV18, and CY7C1615KV18 are 1.8-V
synchronous pipelined SRAMs, equipped with QDR
®
II
architecture. QDR II architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II architecture has separate data inputs and
data outputs to completely eliminate the need to “turn around”
the data bus that exists with common I/O devices. Each port can
be accessed through a common address bus. Addresses for
read and write addresses are latched on alternate rising edges
of the input (K) clock. Accesses to the QDR II read and write
ports are completely independent of one another. To maximize
data throughput, both read and write ports are equipped with
DDR interfaces. Each address location is associated with four
18-bit
words
(CY7C1613KV18),
or
36-bit
words
(CY7C1615KV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click
here.
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■
Selection Guide
Description
Maximum operating frequency
Maximum operating current
× 18
× 36
333 MHz
333
760
1010
300 MHz
300
710
950
250 MHz
250
Not Offered
830
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-44273 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 2, 2018
CY7C1613KV18/CY7C1615KV18
Logic Block Diagram – CY7C1613KV18
D
[17:0]
18
Read Add. Decode
Write Add. Decode
A
(20:0)
21
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
21
A
(20:0)
2M x 18 Array
2M x 18 Array
2M x 18 Array
2M x 18 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
CQ
DOFF
Read Data Reg.
72
V
REF
WPS
BWS
[1:0]
36
Control
Logic
36
Reg.
Reg.
Reg. 18
18
18
18
CQ
18
Q
[17:0]
Logic Block Diagram – CY7C1615KV18
36
D
[35:0]
Read Add. Decode
Write Add. Decode
A
(19:0)
20
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
20
A
(19:0)
1M x 36 Array
1M x 36 Array
1M x 36 Array
1M x 36 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
CQ
DOFF
Read Data Reg.
144
V
REF
WPS
BWS
[3:0]
72
Control
Logic
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q
[35:0]
Document Number: 001-44273 Rev. *L
Page 2 of 32
CY7C1613KV18/CY7C1615KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 7
Byte Write Operations ................................................. 7
Single Clock Mode ...................................................... 7
Concurrent Transactions ............................................. 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
PLL .............................................................................. 7
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ............................................... 10
Write Cycle Descriptions ............................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port ....................................................... 12
Performing a TAP Reset ........................................... 12
TAP Registers ........................................................... 12
TAP Instruction Set ................................................... 12
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
TAP Electrical Characteristics ...................................... 15
TAP AC Switching Characteristics ............................... 16
TAP Timing and Test Conditions .................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Order .................................................... 19
Power Up Sequence in QDR II SRAM ........................... 20
Power Up Sequence ................................................. 20
PLL Constraints ......................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
DC Electrical Characteristics ..................................... 21
AC Electrical Characteristics ..................................... 23
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 26
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagram ............................................................ 28
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC® Solutions ...................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Document Number: 001-44273 Rev. *L
Page 3 of 32
CY7C1613KV18/CY7C1615KV18
Pin Configurations
The pin configurations for CY7C1613KV18, and CY7C1615KV18 follow:
[1]
Figure 1. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1613KV18 (8 M × 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
A
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/288M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
CY7C1615KV18 (4 M × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
NC/288M
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
A
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
A
10
A
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Note
1. NC/288M is not connected to the die and can be tied to any voltage level.
Document Number: 001-44273 Rev. *L
Page 4 of 32
CY7C1613KV18/CY7C1615KV18
Pin Definitions
Pin Name
D
[x:0]
I/O
Pin Description
Input-
Data input signals.
Sampled on the rising edge of K and K clocks when valid write operations are active.
Synchronous CY7C1613KV18
D
[17:0]
CY7C1615KV18
D
[35:0]
Input-
Write port select
Active low.
Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
[x:0]
.
Input-
Byte write select (BWS) 0, 1, 2, and 3
Active low.
Sampled on the rising edge of the K and K clocks
Synchronous when write operations are active. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1613KV18
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1615KV18
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
,
BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27].
All the byte write selects are sampled on the same edge as the data. Deselecting a BWS ignores the
corresponding byte of data and it is not written into the device.
Input-
Address inputs.
Sampled on the rising edge of the K clock during active read and write operations.
Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 8 M × 18 (4 arrays each of 2 M × 18) for CY7C1613KV18 and 4 M × 36 (4 arrays each of
1 M × 36) for CY7C1615KV18. Therefore, only 21 address inputs are needed to access the entire
memory array of CY7C1613KV18 and 20 address inputs for CY7C1615KV18. These inputs are ignored
when the appropriate port is deselected.
Outputs-
Data output signals.
These pins drive out the requested data when the read operation is active. Valid
Synchronous data is driven out on the rising edge of the C and C clocks during read operations, or K and K when in
single clock mode. On deselecting the read port, Q
[x:0]
are automatically tristated.
CY7C1613KV18
Q
[17:0]
CY7C1615KV18
Q
[35:0]
Input-
Read port select
Active low.
Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tri-stated following the next rising edge
of the C clock. Each read access consists of a burst of four sequential transfers.
Input Clock
Positive input clock for output data.
C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See
Application Example on page 8
for further details.
Negative input clock for output data.
C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See
Application Example on page 8
for further details.
Positive input clock input.
The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated on the rising
edge of K.
Negative input clock input.
K is used to capture synchronous inputs being presented to the device
and to drive out data through Q
[x:0]
when in single clock mode.
CQ referenced with respect to C.
This is a free-running clock and is synchronized to the input clock
for output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the
Switching Characteristics on page 24.
CQ referenced with respect to C.
This is a free-running clock and is synchronized to the input clock
for output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the
Switching Characteristics on page 24.
Output impedance matching input.
This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to V
DDQ
, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
Page 5 of 32
WPS
BWS
0
,
BWS
1
,
BWS
2
,
BWS
3
A
Q
[x:0]
RPS
C
C
Input Clock
K
Input Clock
K
CQ
Input Clock
Echo Clock
CQ
Echo Clock
ZQ
Input
Document Number: 001-44273 Rev. *L
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