LD6805 series
119
4-1
Low-dropout regulators, high PSRR, 150 mA
Rev. 4 — 7 June 2013
Product data sheet
1. Product profile
1.1 General description
The LD6805 series is a small-size Low DropOut regulator (LDO) family with ultra high
Power Supply Rejection Ratio (PSRR) of 75 dB. The voltage drop is 250 mV at 150 mA
current rating. Operating voltages can range from 2.3 V to 5.5 V. Each device has a fixed
output voltage V
O(nom)
between 1.2 V and 3.6 V.
The LD6805K/xxH devices show a high-ohmic state (3-state) at the output pin when set to
disabled mode. The LD6805K/xxP devices contain a pull-down switching transistor to
provide a low-ohmic output state (auto discharge function) in disabled mode.
The LD6805 series devices are available in a DFN1010C-4 (SOT1194-1) plastic package
with a size of 1
1
0.55 mm. The devices are ideal for use in portable applications
requiring component miniaturization.
SO
T
1.2 Features and benefits
High PSRR
Overcurrent protection
Auto discharge or high-ohmic output state when disabled
Low quiescent current (0.1
A)
in shutdown mode
High-level ElectroStatic Discharge (ESD) protection (6 kV Human Body Model (HBM))
DFN1010C-4 (SOT1194-1) plastic package with a size of 1
1
0.55 mm
Pb-free, Restriction of Hazardous Substances (RoHS) compliant, free of halogen and
antimony (dark green compliant)
1.3 Applications
Smartphones
Mobile handsets
Digital still cameras
Tablet PCs
Mobile internet devices
Portable media players
1.4 Quick reference data
I
O
= 150 mA
PSRR = 75 dB at 1 kHz
RMS noise V
n(o)RMS
= 40
V
at 10 Hz to 100 kHz
t
startup(reg)
= 150
s
V
I
= 2.3 V to 5.5 V
V
O
= 1.2 V to 3.6 V
Dropout voltage V
do
= 250 mV
at I
O
= 150 mA
Quiescent current I
q
= 35
A
at 0 mA
NXP Semiconductors
LD6805 series
Low-dropout regulators, high PSRR, 150 mA
2. Pinning information
2.1 Pinning
LD6805
IN
4
3
EN
OUT
1
2
GND
001aan948
Transparent top view
Fig 1.
Pin configuration for DFN1010C-4 (SOT1194-1)
2.2 Pin description
Table 1.
Symbol
OUT
GND
EN
IN
i.c.
[1]
Pin description for DFN1010C-4 (SOT1194-1)
Pin
1
2
3
4
TAB
Description
regulator output voltage
supply ground
device enable input; active HIGH
regulator input voltage
internal connected
[1]
The TAB is GND level (it is placed on the reverse side of the IC).
It is recommended to connect the TAB to GND. Leaving it unconnected is also allowed but it may result in
lower thermal performance.
3. Ordering information
Table 2.
Ordering information
Package
Name
LD6805 series
DFN1010C-4
Description
plastic thermal enhanced ultra thin small outline package;
no leads; 4 terminals; body 1
1
0.55 mm
Version
SOT1194-1
Type number
Further ordering options see
Section 3.1 “Ordering options”.
LD6805_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 7 June 2013
2 of 22
NXP Semiconductors
LD6805 series
Low-dropout regulators, high PSRR, 150 mA
3.1 Ordering options
Further information on output voltage is available on request; see
Section 20 “Contact
information”.
An explanation of high-ohmic and pull-down type is in
Section 4 “Block
diagram”.
Table 3.
Type number extension of high-ohmic output
Nominal output
voltage V
O(nom)
1.2 V
1.3 V
1.4 V
1.5 V
1.6 V
1.8 V
1.85 V
2.0 V
2.1 V
Type number
LD6805K/22H
LD6805K/23H
LD6805K/25H
LD6805K/28H
LD6805K/29H
LD6805K/30H
LD6805K/31H
LD6805K/33H
LD6805K/36H
Nominal output
voltage V
O(nom)
2.2 V
2.3 V
2.5 V
2.8 V
2.9 V
3.0 V
3.1 V
3.3 V
3.6 V
Type number
LD6805K/12H
LD6805K/13H
LD6805K/14H
LD6805K/15H
LD6805K/16H
LD6805K/18H
LD6805K/185H
LD6805K/20H
LD6805K/21H
Table 4.
Type number extension of pull-down output
Nominal output
voltage V
O(nom)
1.2 V
1.3 V
1.4 V
1.5 V
1.6 V
1.8 V
2.0 V
2.1 V
2.2 V
Type number
LD6805K/23P
LD6805K/25P
LD6805K/26P
LD6805K/28P
LD6805K/29P
LD6805K/30P
LD6805K/31P
LD6805K/33P
LD6805K/36P
Nominal output
voltage V
O(nom)
2.3 V
2.5 V
2.6 V
2.8 V
2.9 V
3.0 V
3.1 V
3.3 V
3.6 V
Type number
LD6805K/12P
LD6805K/13P
LD6805K/14P
LD6805K/15P
LD6805K/16P
LD6805K/18P
LD6805K/20P
LD6805K/21P
LD6805K/22P
LD6805_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 7 June 2013
3 of 22
NXP Semiconductors
LD6805 series
Low-dropout regulators, high PSRR, 150 mA
4. Block diagram
Fig 2.
Block diagram of LD6805K/xxP (auto discharge function)
Fig 3.
Block diagram of LD6805K/xxH
LD6805_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 7 June 2013
4 of 22
NXP Semiconductors
LD6805 series
Low-dropout regulators, high PSRR, 150 mA
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol
V
I
V
EN
V
O
P
tot
T
stg
T
j
T
amb
V
ESD
Parameter
input voltage
voltage on pin EN
output voltage
total power dissipation
storage temperature
junction temperature
ambient temperature
electrostatic discharge
voltage
human body model level 6
machine model class 3
[2]
[3]
[1]
Conditions
4 ms transient
Min
0.5
0.5
0.5
-
55
40
40
-
-
Max
+6
+6
+6
400
+150
+125
+85
6
400
Unit
V
V
V
mW
C
C
C
kV
V
[1]
The (absolute) maximum power dissipation depends on the junction temperature T
j
. Higher power
dissipation is allowed with lower ambient temperatures. The conditions to determine the specified values
are T
amb
= 25
C
and the use of a two-layer Printed-Circuit Board (PCB).
According to IEC 61340-3-1.
According to JESD22-A115C.
[2]
[3]
6. Recommended operating conditions
Table 6.
Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
T
amb
T
j
Pin IN
V
I
Pin EN
V
EN
Pin OUT
V
O
C
L(ext)
[1]
Parameter
ambient temperature
junction temperature
input voltage
voltage on pin EN
output voltage
external load
capacitance
Conditions
Min
40
-
2.3
0
0.5
[1]
Typ
-
-
-
-
-
1.0
Max
+85
+125
5.5
V
I
V
I
+ 0.3
-
Unit
C
C
V
V
V
F
0.7
See
Section 10.1 “Capacitor values”.
LD6805_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 7 June 2013
5 of 22
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
