Operating Junction Temperature Range ......... -55NC to +150NC
Storage Temperature Range............................ -65NC to +160NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted. Signal applied
to CIN or DIN/DIN only when selected as the reference clock.) (Note 1)
PARAMETER
Supply Current with PLL
Enabled (Note 2)
Supply Current with PLL
Bypassed (Note 2)
SYMBOL
I
CC
CONDITIONS
Configured with LVPECL outputs
Configured with LVDS outputs
Configured with LVPECL outputs
Configured with LVDS outputs
MIN
TYP
150
270
100
220
MAX
200
360
UNITS
mA
mA
LVCMOS/LVTTL CONTROL INPUTS (IN_SEL, DM, DF, DA, DB, DC, PLL_BP, QA_CTRL1, QA_CTRL2, QB_CTRL,
QC_CTRL)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Reference Clock Input
Frequency
Input Amplitude Range
Input High Current
Input Low Current
Reference Clock Input Duty-
Cycle Distortion
Input Capacitance
DIFFERENTIAL CLOCK INPUT (DIN,
DIN)
(Note 4)
Differential Input Frequency
f
REF
Input Bias Voltage
Input Differential Voltage Swing
Single-Ended Voltage Range
Input Differential Impedance
Differential Input Capacitance
2
V
CMI
15
V
CC
-
1.8
150
V
CC
-
2.0
80
100
1.5
V
CC
-
1.3
1800
V
CC
-
0.7
120
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
V
IN
= V
CC
V
IN
= 0V
-80
2.0
0.8
80
V
V
FA
FA
LVCMOS/LVTTL CLOCK INPUT (CIN)
f
REF
Internally AC-coupled (Note 3)
V
IN
= V
CC
V
IN
= 0V
15
1.2
-80
40
1.5
350
60
160
3.6
80
MHz
V
P-P
FA
FA
%
pF
MHz
V
mV
P-P
V
I
pF
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted. Signal applied
to CIN or DIN/DIN only when selected as the reference clock.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
1.475
0.925
250
400
25
1.125
1.3
25
80
Short together
Short to ground
V
Q_
= V
Q_
= 0V to V
CC
20% to 80%
PLL enabled
PLL bypassed (Note 6)
V
CC
-
1.13
V
CC
-
1.85
0.5
V
O
= 0V to V
CC
20% to 80%, differential load = 100I
PLL enabled
PLL bypassed (Note 6)
f
VCO
25MHz crystal
input
12kHz to 20MHz
1.875MHz to 20MHz
48
48
100
3
6
10
160
50
50
V
CC
-
0.98
V
CC
-
1.70
0.7
10
140
50
50
625
130
0.34
0.14
0.34
-56
6
dBc
ps
P-P
1.0
ps
RMS
240
52
V
CC
-
0.83
V
CC
-
1.55
0.9
240
52
140
UNITS
V
V
mV
mV
V
mV
I
mA
FA
ps
%
LVDS OUTPUTS (QA[4:0],
QA[4:0],
QB[2:0],
QB[2:0],
QC,
QC)
(Note 5)
Output High Voltage
V
OH
Output Low Voltage
Differential Output Voltage
Change in Magnitude
of Differential Output for
Complementary States
Output Offset Voltage
Change in Magnitude of
Output Offset Voltage for
Complementary States
Differential Output Impedance
Output Current
Output Current When Disabled
Output Rise/Fall Time
Output Duty-Cycle Distortion
V
OL
|V
OD
|
D|V
OD
|
V
OS
D|V
OS
|
MAX3612
LVPECL OUTPUTS (QA[4:0],
QA[4:0],
QB[2:0],
QB[2:0],
QC,
QC)
(Note 7)
Output High Voltage
Output Low Voltage
Output-Voltage Swing
(Single-Ended)
Output Current When Disabled
Output Rise/Fall Time
Output Duty-Cycle Distortion
PLL SPECIFICATIONS
VCO Frequency Range
PLL Jitter Transfer Bandwidth
Integrated Phase Jitter at
156.25MHz Output
Supply-Noise Induced Phase
Spur
Determinisitic Jitter Induced by
Power-Supply Noise
MHz
kHz
V
OH
V
OL
V
V
V
P-P
FA
ps
%
RJ
RMS
25MHz LVCMOS or differential input
(Note 8)
(Note 9)
(Note 9)
3
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
MAX3612
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted. Signal applied
to CIN or DIN/DIN only when selected as the reference clock.) (Note 1)
PARAMETER
Nonharmonic and Subharmonic
Spurs
SYMBOL
(Note 10)
f
OFFSET
= 1kHz
f
OFFSET
= 10kHz
SSB Phase Noise at 312.5MHz
f
OFFSET
= 100kHz
f
OFFSET
= 1MHz
f
OFFSET
R
10MHz
f
OFFSET
= 1kHz
f
OFFSET
= 10kHz
SSB Phase Noise at 156.25MHz
f
OFFSET
= 100kHz
f
OFFSET
= 1MHz
f
OFFSET
R
10MHz
f
OFFSET
= 1kHz
f
OFFSET
= 10kHz
SSB Phase Noise at 125MHz
f
OFFSET
= 100kHz
f
OFFSET
= 1MHz
f
OFFSET
R
10MHz
CONDITIONS
MIN
TYP
-70
-115
-116
-122
-139
-149
-122
-123
-129
-145
-152
-123
-124
-130
-147
-153
dBc/
Hz
dBc/
Hz
dBc/
Hz
MAX
UNITS
dBc
Note 1:
A series resistor of up to 10.5I is allowed between V
CC
and V
CCA
for filtering supply noise when system power-supply
tolerance is V
CC
= 3.3V
Q5%.
See Figure 2.
Note 2:
Measured with all outputs enabled and unloaded.
Note 3:
CIN can be AC- or DC-coupled. See Figure 7. Input high voltage must be ≤ V
CC
to +0.3V.
Note 4:
DIN can be AC- or DC-coupled. See Figure 9.
Note 5:
Measured with 100I differential load.
Note 6:
Measured with crystal input, or with 50% duty cycle LVCMOS, or differential input.
Note 7:
Measured with output termination of 50I to V
CC
- 2V or Thevenin equivalent.
Note 8:
Measured using LVCMOS/LVTTL input with slew rate
R
1.0V/ns, or differential input with slew rate
R
0.5V/ns.
Note 9:
Measured at 156.25MHz output with 200kHz, 50mV
P-P
sinusoidal signal on the supply using the crystal input and
the power-supply filter shown in Figure 2. See the
Typical Operating Characteristics
for other supply noise frequen-
cies. Deterministic jitter is calculated from the measured power-supply-induced spurs. For more information, refer to
Application Note 4461:
HFAN-04.5.5: Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers.
Note 10:
Measured with all outputs enabled and all three banks at different frequencies.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
