Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges
at Ta = -40 to +85°C, VSS = 0V
Parameter
Supply voltage
Symbol
VDD
VLCD
VLCD
Output voltage
Input voltage
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
Input high level voltage
VIH1
VIH2
Input low level voltage
Recommended external resistance
Recommended external
capacitance
Guaranteed oscillation range
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
DO output delay time
DO rise time
fOSC
tds
tdh
tcp
tcs
tch
tφH
tφL
tdc
tdr
OSC
CL, DI
CL, DI
CE, CL
CE, CL
CE, CL
CL
CL
DO RPU=4.7kΩ, CL=10pF *1
DO RPU=4.7kΩ, CL=10pF *1
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
[Figure 2]
25
160
160
160
160
160
160
160
1.5
1.5
VIL
ROSC
COSC
VDD
VLCD, When the display contrast adjustment
circuit is used
VLCD , When the display contrast adjustment
circuit is not used
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
CE, CL, DI, INH
KI1 to KI5
CE, CL, DI, INH, KI1 to KI5
OSC
OSC
0
0.8VDD
0.6VDD
0
43
680
50
100
Conditions
min
4.5
7.0
4.5
VLCD4
+4.5
3/4(VLCD0
-VLCD4)
2/4(VLCD0
-VLCD4)
1/4(VLCD0
-VLCD4)
Ratings
typ
max
6.0
11.0
11.0
VLCD
VLCD0
VLCD0
VLCD0
1.5
6.0
VDD
0.2VDD
V
V
V
kΩ
pF
kHz
ns
ns
ns
ns
ns
ns
ns
μs
μs
V
V
unit
V
Note:
*1.
Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and the
load capacitance CL.
No.6370-2/38
LC75808W
Electrical Characteristics
for the Allowable Operating Ranges
Parameter
Hysteresis
Power-down detection
voltage
Input high level current
Input low level current
Input floating voltage
Pull-down resistance
Output off leakage current
Output high level voltage
IIH
IIL
VIF
RPD
IOFFH
VOH1
VOH2
VOH3
VOH4
Output low level voltage
VOL1
VOL2
VOL3
VOL4
VOL5
Output middle level voltage
*2
VMID2
COM1 to COM10: IO=±100μA
VMID1
CE, CL, DI, INH: VI=6.0V
CE, CL, DI, INH: VI=0V
KI1 to KI5
KI1 to KI5: VDD=5.0V
DO: VO=6.0V
S1 to S60: IO=-20μA
COM1 to COM10: IO=-100μA
KS1 to KS6: IO=-500μA
P1 to P4: IO=-1mA
S1 to S60: IO=20μA
COM1 to COM10: IO=100μA
KS1 to KS6: IO=25μA
P1 to P4: IO=1mA
DO: IO=1mA
S1 to S60: IO=±20μA
2/4(VLCD0
-VLCD4)
-0.6
3/4(VLCD0
-VLCD4)
-0.6
VMID3
COM1 to COM10: IO=±100μA
1/4(VLCD0
-VLCD4)
-0.6
Oscillator frequency
Current drain
fOSC
IDD1
IDD2
ILCD1
ILCD2
ILCD3
OSC: ROSC=43kΩ, COSC=680pF
VDD: Sleep mode
VDD: VDD=6.0V, outputs open, fOSC=50kHz
VLCD: Sleep mode
VLCD: VLCD=11.0V, Outputs open, fOSC=50kHz
(When the display contrast adjustment circuit is used.)
VLCD: VLCD=11.0V, Outputs open, fOSC=50kHz
(When the display contrast adjustment circuit is not
used.)
500
250
40
50
0.1
0.2
0.5
VLCD0-0.6
VLCD0-0.6
VDD-1.0
VDD-1.0
VLCD4+0.6
VLCD4+0.6
1.5
1.0
0.5
2/4(VLCD0
-VLCD4)
+0.6
3/4(VLCD0
-VLCD4)
+0.6
1/4(VLCD0
-VLCD4)
+0.6
60
100
500
5
1000
μA
kHz
V
V
VDD-0.5
VDD-0.2
V
50
100
-5.0
0.05VDD
250
6.0
Symbol
VH
VDET
Conditions
min
CE, CL, DI, INH, KI1 to KI5
2.5
Ratings
typ
0.1VDD
3.0
3.5
5.0
max
V
V
μA
μA
V
kΩ
μA
unit
250
500
Note:
*2
Excluding the bias voltage generation divider resistor built into VLCD0, VLCD1, VLCD2, VLCD3, and
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