UTI760A RTS Remote Terminal for Stores
F
EATURES
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Complete MIL-STD-1760A Notice I through III
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remote terminal interface
1K x 16 of on-chip static RAM for message data,
completely accessible to host
Self-test capability, including continuous loop-back
compare
Programmable memory mapping via pointers for
efficient use of internal memory, including buffering
multiple messages per subaddress
RT-RT Terminal Address Compare
Command word stored with incoming data for
enhanced data management
User selectable RAM Busy (RBUSY) signal for slow
or fast processor interfacing
Full military operating temperature range, -55°C to
+125°C, screened to the specific test methods listed in
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Table I of MIL-STD-883, Method 5004, Class B, also
Standard Military Drawing available
Available in 68-pin pingrid array package
I
NTRODUCTION
The UT1760A RTS is a monolithic CMOS VLSI solution
to the requirements of the dual-redundant MIL-STD-1553B
interface as specified by MIL-STD-1760A. Designed to
reduce cost and space in the mission stores interface, the
RTS integrates the remote terminal logic with a user-
configured 1K x 16 static RAM. In addition, the RTS has a
flexible subsystem interface to permit use with most
processors or controllers.
The RTS provides all protocol, data handling, error
checking, and memory control functions, as well as
comprehensive self-test capabilities. The RTS’s memory
meets all of a mission store’s message storage needs through
user-defined memory mapping. This memory-mapped
architecture allows multiple message buffering at
MCSA(4:0)
MODE CODE/
SUBADDRESS
OUTPUT MULTIPLEXING AND
SELF-TEST WRAPAROUND LOGIC
RTA(4:0)
REMOTE TERMINAL
ADDRESS
CONTROL
INPUTS
OUT
STATUS
OUTPUTS
DECODER
COMMAND
RECOGNITION
CONTROL AND
ERROR LOGIC
1K X 16 RAM
ADDR(9:0)
MUX
ENCODER
PTR REGISTER
CLOCK AND RESET 12MHz
LOGIC
RESET
2MHz
Figure 1. UT1760A RTS Functional Block Diagram
IN
OUT
DECODER
IN
DATA(15:0)
RTS-1
Table of Contents
1.0
ARCHITECTURE AND OPERATION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Memory Map and Host Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 RTS RAM Pointer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Internal Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Mode Code and Subaddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 MIL-STD-1760A Subaddress and Mode Code Definitions . . . . . . . . . . . . . . . 9
1.6 Terminal Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.7 Internal Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.8 Power-up and Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.9 Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.10 RT-RT Transfer Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.11 Illegal Command Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
MEMORY MAP EXAMPLE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PIN IDENTIFICATION AND DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . .16
MAXIMUM AND RECOMMENDED OPERATING CONDITIONS22
DC ELECTRICAL CHARACTERISTICS.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
AC ELECTRICAL CHARACTERISTICS.
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PACKAGE OUTLINE DRAWING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.0
3.0
4.0
5.0
6.0
7.0
RTS-2
1.0 A
RCHITECTURE
A
ND
O
PERATION
The UT1760A RTS is an interface device linking a MIL-
STD-1553 serial data bus and a host microprocessor system.
The RTS’s MIL-STD-1553B interface includes encoding/
decoding logic, error detection, command recognition, 1K
x 16 of SRAM, pointer registers, clock, and reset circuits.
Illegal subaddress circuitry makes the RTS MIL-STD-
1760A-specific.
to its own internal RAM, it asserts the RBUSY signal to
alert the host. The RBUSY signal is programmable via the
internal Control Register to be asserted either 5.7ms or
2.7ms prior to the RTS needing access to its internal RAM.
The RTS stores MIL-STD-1760A messages in 1K x 16 of
on-chip RAM. For efficient use of the 1K x 16 memory on
the RTS, the host programs a set of pointers to map where
the 1760A message is stored. The RTS uses the upper 64
words (address 3C0 (hex) through 3FF (hex)) as pointers.
The RTS provides pointers for all 30 receive subaddresses,
all 30 transmit subaddresses, and four mode code
commands with associated data words as defined in
MIL-STD-1553B. The remaining 960 words of memory
contain receive, transmit, and mode code data in a
host-defined structure.
1.1 Memory Map and Host Memory Interface
The host can access the 1K x 16 RAM memory like a
standard RAM device through the 10-bit address and 16-bit
data buses. The host uses the Chip Select (CS), Read/Write
(RD/WR), and Output Enable (OE) signals to control data
transfer to and from memory. When the RTS requires access
RTS Memory Map
Message
Storage
Locations
000 (hex)
3BF(hex)
15 MSB
0 LSB
Receive
Message
Pointers
(3C1 TO 3DE)
XMIT VECTOR WORD MODE CODE (W/DATA)
RCV SUBADDRESS 01
3C0 (hex)
3C1 (hex)
RCV SUBADDRESS 30
SYNCHRONIZE MODE CODE (W/DATA)
15 MSB
0 LSB
3DE (hex)
3DF (hex)
Transmit
Message
Pointers
(3E1 TO 3FE)
XMIT LAST COMMAND MODE CODE (W/DATA)
XMT SUBADDRESS 01
3E0 (hex)
3E1 (hex)
XMT SUBADDRESS 30
XMT BIT WORD MODE CODE (W/DATA)
15 MSB
Figure 2. RTS Memory Map
0 LSB
3FE (hex)
3FF (hex)
RTS-3
MESSAGE INDEX
15 (MSB)
Message Index:
Defines the maximum
messages buffered for the
given subaddress.
10
9
MESSAGE DATA ADDRESS
0 (LSB)
Message Data Address:
Indicates the starting memory
address for incoming message
storage.
Figure 3. Message Pointer Structure
1.2 RTS RAM Pointer Structure
The RAM 16-bit pointers have a 6-bit index field and a
10-bit address field. The 6-bit index field allows for the
storage of up to 64 messages per subaddress. A message
consists of the 1553 command word and its associated
data words.
The 16-bit pointer for Transmit Last Command Mode Code
is located at memory location 3E0 (hex). The Transmit Last
Command Mode Code pointer buffers up to 63 command
words. An example of command word storage follows:
Example:
3E0 (hex)
Contents = FC00 (hex)
The Transmit Last Command Mode Code has Address Field
boundary conditions for the location of command word
buffers. The host can allocate a maximum 63 sequential
locations following the Address Field starting address. For
proper operation, the Address Field must start on an I x 40
(hex) address boundary, where I is greater than or equal to
zero and less than or equal to 14. A list of valid Index and
Address Fields follows:
I
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Valid Index Fields
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
Valid Address Fields
000 (hex) to 03F(hex)
040 (hex) to 07F (hex)
080 (hex) to 0BF(hex)
0C0 (hex) to 0FF (hex)
100 (hex) to 13F (hex)
140 (hex) to 17F (hex)
180 (hex) to 1BF (hex)
1C0 (hex) to 1FF (hex)
200 (hex) to 23F (hex)
240 (hex) to 27F (hex)
280 (hex) to 2BF (hex)
2C0 (hex) to 2FF (hex)
300 (hex) to 33F (hex)
340 (hex) to 37F (hex)
380 (hex) to 3BF (hex)
11 1111 00 0000 0000
Address Field = 000 (hex)
Index Field = 3F (hex)
First command word storage location (3E0 = F801):
Address Field = 001 (hex)
Index Field = 3E (hex)
Sixty-third command word storage location
(3E0 = 003F):
Address Field = 03F (hex)
Index Field = 00 (hex)
Sixty-fourth command word storage location (3E0 = 003F)
(previous command word overwritten):
Address Field = 03F (hex)
Index Field = 00 (hex)
RTS-4
Subaddress/Mode Code
Transmit Vector Word Mode Code
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
Receive Subaddress
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
RAM Location
3C0 (hex)
3C1 (hex)
3C2 (hex)
3C3 (hex)
3C4 (hex)
3C5 (hex)
3C6 (hex)
3C7 (hex)
3C8 (hex)
3C9 (hex)
3CA (hex)
3CB (hex)
3CC (hex)
3CD (hex)
3CE (hex)
3CF (hex)
3D0 (hex)
3D1 (hex)
3D2 (hex)
3D3 (hex)
3D4 (hex)
3D5 (hex)
3D6 (hex)
3D7 (hex)
3D8 (hex)
3D9 (hex)
3DA (hex)
3DB (hex)
3DC (hex)
3DD (hex)
3DE (hex)
3DF (hex)
Subaddress/Mode Code
Transmit Last Command Mode Code
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
Transmit Subaddress
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
RAM Location
3E0 (hex)
3E1 (hex)
3E2 (hex)
3E3 (hex)
3E4 (hex)
3E5 (hex)
3E6 (hex)
3E7 (hex)
3E8 (hex)
3E9 (hex)
3EA (hex)
3EB (hex)
3EC (hex)
3ED (hex)
3EE (hex)
3EF (hex)
3F0 (hex)
3F1 (hex)
3F2 (hex)
3F3 (hex)
3F4 (hex)
3F5 (hex)
3F6 (hex)
3F7 (hex)
3F8 (hex)
3F9 (hex)
3FA (hex)
3FB (hex)
3FC (hex)
3FD (hex)
3FE (hex)
3FF (hex)
Receive Subaddress
30
Synchronize w/Data Word Mode Code
Transmit Subaddress
30
Transmit Bit Word Mode Code
1.3 Internal Registers
The RTS uses two internal registers to allow the host to
control the RTS operation and monitor its status. The host
uses the Control (CTRL) signal along with Chip Select (CS),
Read/Write (RD/WR), and Output Enable (OE) to read the
16-bit Status Register or write to the 13-bit Control Register.
No address data is needed to select a register. The Control
Register toggles bits in the MIL-STD-1553B status word,
enables the biphase inputs, recognizes broadcast
commands, selects Notice I and II or III, determines RAM
Busy (RBUSY) timing, selects disconnect or terminal active
flag, and puts the part in self-test mode. The Status Register
supplies operational status of the UT1760A RTS to the host.
These registers must be initialized before attempting RTS
operation. Internal registers can be accessed while RBUSY
is active.
RTS-5
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