Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
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the references to Nexperia, as shown below.
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- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
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-
© Nexperia B.V. (year). All rights reserved.
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74ALVCH16952
16-bit registered transceiver; 3-state
Rev. 02 — 27 April 2006
Product data sheet
1. General description
The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting
registered transceiver. Two 8-bit back to back registers store data flowing in both
directions between two bidirectional buses. Data applied to the inputs is entered and
stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock enable
(nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but is only
accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow from A
inputs to B outputs is the same as for B inputs to A outputs.
2. Features
I
CMOS low-power consumption
I
Multibyte flow-through pinout architecture
I
Low inductance, multiple center power and ground pins for minimum noise and ground
bounce
I
Direct interface with TTL levels
I
Output drive capability 50
Ω
transmission lines at 85
°C
I
Complies with JEDEC standard JESD8-B
3. Quick reference data
Table 1.
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 2.5 ns.
Symbol Parameter
t
PHL
,
t
PLH
propagation delay
nCPBA to nAn; nCPAB to nBn V
CC
= 3.3 V; C
L
= 50 pF
V
CC
= 2.5 V; C
L
= 30 pF
f
max
C
i
C
PD
[1]
Conditions
Min
-
-
-
-
[1]
Typ
3.2
3.2
350
3.0
30
Max Unit
-
-
-
-
-
ns
ns
MHz
pF
pF
maximum input clock
frequency
input capacitance
V
CC
= 3.3 V
power dissipation capacitance per buffer; V
I
= GND to V
CC
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = number of inputs switching;
Σ(C
L
×
V
CC2
×
f
o
) = sum of outputs.
-
Philips Semiconductors
74ALVCH16952
16-bit registered transceiver; 3-state
4. Ordering information
Table 2.
Ordering information
Package
Temperature range Name
DGG
−40 °C
to +85
°C
TSSOP56
Description
plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
Version
SOT364-1
Type number
5. Functional diagram
5
6
8
9
10
12
13
14
52
51
49
48
47
45
44
43
15
16
17
19
20
22
23
24
42
41
40
38
37
36
34
33
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
1OEBA
1OEAB
1CEAB
1CEBA
1CPAB
1CPBA
56 1
3
54 2
55
2OEBA
2OEAB
2CEAB
2CEBA
2CPAB
2CPBA
29 28 26 31 27 30
001aae552
Fig 1. Logic symbol
74ALVCH16952_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 27 April 2006
2 of 17
Philips Semiconductors
74ALVCH16952
16-bit registered transceiver; 3-state
1OEBA
1CEBA
1CPBA
1OEAB
1CEAB
1CPAB
56
54
55
1
3
2
29
1EN3
G1
1C5
EN4
G2
2C6
EN9
G7
7C11
EN10
G8
8C12
3
6D
5D
4
51
49
48
47
45
44
43
9
12D
11D
10
41
40
38
37
36
34
33
001aae550
2OEBA
31
2CEBA
30
2CPBA
28
2OEAB
26
2CEAB
27
2CPAB
1A0
5
52
1B0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
6
8
9
10
12
13
14
15
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
42
2A1
2A2
2A3
2A4
2A5
2A6
2A7
16
17
19
20
21
23
24
2B1
2B2
2B3
2B4
2B5
2B6
2B7
Fig 2. IEC logic symbol
V
CC
data input
to internal circuit
001aad245
Fig 3. Bus hold circuit
74ALVCH16952_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 27 April 2006
3 of 17
Philips Semiconductors
74ALVCH16952
16-bit registered transceiver; 3-state
CEAB
CPAB
OEAB
CEBA
CPBA
OEBA
Q
A0
D
CP
Q
D
CP
8 IDENTICAL CHANNELS
B0
TO 7 OTHER CHANNELS
001aae549
Fig 4. Schematic diagram (one section)
74ALVCH16952_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 27 April 2006
4 of 17
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