74ABT841
10-bit bus interface latch; 3-state
Rev. 4 — 7 November 2011
Product data sheet
1. General description
The 74ABT841 high performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT841 bus interface register is designed to provide extra data width for wider
data/address paths of buses carrying parity.
The 74ABT841 consists of ten D-type latches with 3-state outputs. The flip-flops appear
transparent to the data when latch enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW
transition, the data that meets the set-up and hold time is latched.
Data appears on the bus when the output enable (OE) is LOW. When OE is HIGH the
output is in the high-impedance state.
2. Features and benefits
High speed parallel latches
Extra data width for wide address/data paths or buses carrying parity
Ideal where high speed, light loading, or increased fan-in are required with MOS
microprocessors
Broadside pinout
Output capability: +64 mA and
32
mA
Power-up 3-state
Power-up reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
NXP Semiconductors
74ABT841
10-bit bus interface latch; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74ABT841D
74ABT841DB
74ABT841PW
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
Name
SO24
SSOP24
TSSOP24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT137-1
SOT340-1
SOT355-1
Type number
4. Functional diagram
1
13
EN
C1
23
22
21
20
19
18
17
16
15
14
001aae912
2
3
4
5
6
7
8
9
10 11
2
3
1D
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
13
1
LE
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
23 22 21 20 19 18 17 16 15 14
001aae911
4
5
6
7
8
9
10
11
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
D0
2
D
D1
3
D
D2
4
D
D3
5
D
D4
6
D
D5
7
D
D6
8
D
D7
9
D
D8
10
D
D9
11
D
L
LE
13
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
OE
1
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
Q9
001aae913
Fig 3.
Logic diagram
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
2 of 15
NXP Semiconductors
74ABT841
10-bit bus interface latch; 3-state
5. Pinning information
5.1 Pinning
74ABT841
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 LE
001aae910
D8 10
D9 11
GND 12
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Symbol
OE
D0 to D9
GND
LE
Q0 to Q9
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9,10, 11
12
13
23, 22, 21, 20, 19, 18, 17, 16, 15, 14
24
Description
output enable input (active LOW)
data input
ground (0 V)
latch enable input (active falling edge)
data output
positive supply voltage
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
3 of 15
NXP Semiconductors
74ABT841
10-bit bus interface latch; 3-state
6. Functional description
Table 3.
Input
OE
L
L
L
L
H
L
[1]
Function table
[1]
Output
LE
H
H
X
L
nD
L
H
l
h
X
X
Q0 to Q9
L
H
L
H
Z
NC
high-impedance
hold
latched
transparent
Operating mode
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH LE transition;
= HIGH-to-LOW clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
j
T
stg
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
junction temperature
storage temperature
Conditions
[1]
Min
0.5
1.2
0.5
18
50
-
[2]
Max
+7.0
+7.0
+5.5
-
-
128
150
+150
Unit
V
V
V
mA
mA
mA
C
C
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
[1]
-
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
4 of 15
NXP Semiconductors
74ABT841
10-bit bus interface latch; 3-state
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
t/V
T
amb
Recommended operating conditions
Parameter
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
input transition rise and fall rate
ambient temperature
in free air
Conditions
Min
4.5
0
2.0
-
32
-
0
40
Typ
-
-
-
-
-
-
-
-
Max
5.5
V
CC
-
0.8
-
64
5
+85
Unit
V
V
V
V
mA
mA
ns/V
C
9. Static characteristics
Table 6.
Static characteristics
Conditions
Min
V
IK
V
OH
input clamping voltage
HIGH-level output
voltage
V
CC
= 4.5 V; I
IK
=
18
mA
V
I
= V
IL
or V
IH
V
CC
= 4.5 V; I
OH
=
3
mA
V
CC
= 5.0 V; I
OH
=
3
mA
V
CC
= 4.5 V; I
OH
=
32
mA
V
OL
V
OL(pu)
I
I
LOW-level output
voltage
power-up LOW-level
output voltage
input leakage current
V
CC
= 4.5 V; I
OL
= 64 mA;
V
I
= V
IL
or V
IH
V
CC
= 5.5 V; I
O
= 1 mA;
V
I
= GND or V
CC
V
CC
= 5.5 V; V
I
= GND or 5.5 V
control pins
data pins
I
OFF
I
O(pu/pd)
I
OZ
power-off leakage
current
power-up/power-down
output current
V
CC
= 0 V; V
I
or V
O
4.5 V
V
CC
= 2.0 V; V
O
= 0.5 V;
V
I
= GND or V
CC
; OEn HIGH
V
O
= 2.7 V
V
O
= 0.5 V
I
LO
I
O
output leakage current
output current
HIGH-state; V
O
= 5.5 V;
V
CC
= 5.5 V; V
I
= GND or V
CC
V
CC
= 5.5 V; V
O
= 2.5 V
[3]
[2]
[1]
Symbol Parameter
25
C
Typ
0.9
3.5
4.0
2.6
0.42
0.13
Max
-
-
-
-
0.55
0.55
1.2
2.5
3.0
2.0
-
-
40 C
to +85
C
Unit
Min
1.2
2.5
3.0
2.0
-
-
Max
-
-
-
-
0.55
0.55
V
V
V
V
V
V
-
-
-
-
0.01
5
5.0
5.0
1.0
100
100
50
-
-
-
-
1.0
100
100
50
A
A
A
A
OFF-state output current V
CC
= 5.5 V; V
I
= V
IL
or V
IH
-
-
-
180
5.0
5.0
5.0
100
50
50
50
50
-
-
-
180
50
50
50
50
A
A
A
mA
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
5 of 15
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