NB3N2302
3.3V / 5V 5MHz to 133MHz
Frequency Multiplier and
Zero Delay Buffer
Description
The NB3N2302 is a versatile Zero Delay Buffer that operates from
5 MHz to 133 MHz with a 3.3 V or 5 V power supply. It accepts a
reference input and drives a
B1
and a
B2
clock output. The
NB3N2302 has an on−chip PLL which locks to the input reference
clock presented on the REF_IN pin. The PLL feedback is required to
be driven to the FBIN pin and can be obtained by connecting either the
OUT1 or OUT2 pin to the FBIN pin.
The Function Select inputs control the various multiplier output
frequency combinations as shown in Table 1.
Features
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MARKING DIAGRAM
8
1
SOIC−8
D SUFFIX
CASE 751
2302
A
L
Y
W
G
8
3N2302
ALYWG
G
1
•
•
•
•
•
•
•
•
•
•
•
Output Frequency Range: 5 MHz to 133 MHz
Two LVTTL/LVCMOS Outputs
65 ps Typical Jitter OUT2
115 ps Typical Jitter OUT1
25 ps Typical Output−to−Output Skew
Operating Voltage Range: V
DD
= 3.3 V
$5%
or 5 V
$10%
Clock Multiplication of the Reference Input Frequency, See Table 1
for Options
Packaged in 8−Pin SOIC
−40°C
to +85°C Ambient Operating Temperature Range
Ideal for PCI−X and Networking Clocks
These are Pb−Free Devices
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
External feedback connection
to OUT1 or OUT2, not both
FBIN
FS0
FS1
Select Input
Decoding
OUT1
REF_IN
PLL
÷2
OUT2
Figure 1. Simplified Logic Diagram
©
Semiconductor Components Industries, LLC, 2011
October, 2011
−
Rev. 1
1
Publication Order Number:
NB3N2302/D
NB3N2302
FBIN
REF_IN
GND
FS0
1
2
3
4
8
7
6
5
OUT2
V
DD
OUT1
FS1
Figure 2. NB3N2302 Package Pinout (Top View) 8−pin SOIC (150 mil)
Table 1. CLOCK MULTIPLIER SELECT TABLE
FBIN
OUT1
OUT1
OUT1
OUT1
OUT2
OUT2
OUT2
OUT2
FS0
0
1
0
1
0
1
0
1
FS1
0
0
1
1
0
0
1
1
OUT1
2 x REF
4 x REF
REF
8 x REF
4 x REF
8 x REF
2 x REF
16 x REF
OUT2
REF
2 x REF
REF / 2
4 x REF
2 x REF
4 x REF
REF
8 x REF
REF_IN Min
(MHz)
5
5
10
5
5
5
5
5
REF_IN Max
(MHz)
66.5
33.25
133
16.625
33.25
16.625
66.5
8.3125
Table 2. PIN DESCRIPTION
Pin #
1
Pin
Name
FBIN
Type
LVCMOS/LVTTL
Input
Description
Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure
proper functionality. If the trace between FBIN and the output pin being used for feedback
is equal in length to the traces between the outputs and the signal destinations, then the
signals received at the destinations are synchronized to the REF signal input (REF_IN).
Reference Input: The output signals are synchronized to this signal.
Negative supply voltage; Connect to ground, 0 V
Function Select Input: Tie to V
DD
(HIGH, 1) or GND (LOW, 0) as desired per Table 1.
Function Select Input: Tie to V
DD
(HIGH, 1) or GND (LOW, 0) as desired per Table 1.
Output 1: The frequency of the signal provided by this pin is determined by the feedback
signal connected to FBIN, and the FS0:1 inputs (see Table 1).
Positive supply voltage This pin should be bypassed with a 0.1
mF
decoupling capacitor.
Use ferrite beads to help reduce noise for optimal jitter performance.
Output 2: The frequency of the signal provided by this pin is one−half of the frequency of
OUT1. See Table 1.
2
3
4
5
6
7
8
REF_IN
GND
FS0
FS1
OUT1
VDD
OUT2
LVCMOS/LVTTL
Input
Power
LVCMOS/LVTTL
Input
LVCMOS/LVTTL
Input
LVCMOS/LVTTL
Output
Power
LVCMOS/LVTTL
Output
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2
NB3N2302
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Value
> 2 kV
> 200 V
Level 1
UL 94 V−O @ 0.125 in
6910 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index
Table 4. MAXIMUM RATINGS
Symbol
V
DD,
V
IN
T
A
T
stg
T
B
q
JA
P
D
q
JC
T
SOL
Voltage on any pin
Operating Temperature Range,
Storage Temperature Range
Ambient Temperature under Bias
Thermal Resistance (Junction−to−Ambient)
Power Dissipation
Thermal Resistance (Junction−to−Case)
Wave Solder Pb−Free
(Note 2)
SOIC−8
0 lfpm
500 lfpm
SOIC−8
SOIC−8
Commercial
Industrial
Parameter
Condition 1
GND = 0 V
Condition 2
Rating
–0.5 to +7.0
0 to +70
−40
to +85
−65
to +150
–55 to +125
190
130
0.5
42
265
Unit
V
°C
°C
°C
°C/W
W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power
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NB3N2302
Table 5. DC CHARACTERISTICS
V
DD
= 3.3 V
±
5% or 5 V
±
10%, GND = 0 V, T
A
=
−40°C
to +85°C
Symbol
I
DD
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Characteristic
Power Supply Current, 100 MHz, Unloaded Outputs V
DD
= 3.3 V
$
5%
V
DD
= 5 V
$
10%
Output HIGH Voltage I
OH
=
−12
mA
Output LOW Voltage I
OL
= 12 mA
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current, V
IN
= V
DD
Input LOW Current, V
IN
= 0 V
V
DD
= 3.3 V
$
5%
V
DD
= 5 V
$
10%
−40
−80
2.0
0.8
5
5
5
2.4
0.4
Min
Typ
20
25
Max
35
50
Unit
mA
V
V
V
V
mA
mA
Table 6. AC CHARACTERISTICS
V
DD
= 3.3 V
±
5% or 5 V
±
10%, GND = 0 V, T
A
=
−40°C
to +85°C (Note 5)
Symbol
f
IN
f
OUT
t
D
t
r
/t
f
t
INCLK
t
r
/t
f
t
LOCK
t
JC
t
DC
t
pd
t
skew
Input Frequency (Note 3)
Output Frequency, OUT1 15 pF load
Output Duty Cycle @ 1.4 V, 120 MHz, 50% duty cycle in, 15 pF load
Output rise and fall times; 0.8 V to 2.0V, 15 pF load V
DD
= 3.3 V
$
5%
V
DD
= 5 V
$
10%
Input Clock rise and fall time (Note 4)
PLL Lock Time, power supply stable
Cycle−to−cycle Jitter
OUT1,
f
OUT
> 30 MHz
OUT2, f
OUT
> 30 MHz
100
−350
25
350
250
115
65
Characteristic
Min
5
10
40
50
Typ
Max
133
133
60
3.5 / 2.5
2.5 / 1.5
10
1.0
300
300
Unit
MHz
MHz
%
ns
ns
ms
ps
Clock
Cycles
ps
ps
Die “Fave Away” Out Time. 33 MHz reference input suddenly stopped
(0 MHz). Number of cycles provided prior to output falling to < 16 MHz.
Propagation Delay, (Note 10)
Output−to−output skew; (Note 6)
3. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit
configuration). See Table 1.
4. Longer input rise and fall time degrades skew and jitter performance.
5. All AC specifications are measured with a 50
W
transmission line, load terminated with 50
W
to 1.4 V.
6. Skew is measured at 1.4 V on rising edges, all outputs with equal loading.
7. Duty cycle is measured at 1.4 V.
8. 33 MHz reference input suddenly stopped (0 MHz). Number of cycles provided prior to output falling to < 16 MHz.
9. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case.
10. While in lock, propagation delay is measured from REF_IN to OUT1 using < 1 in feedback trace, (See Figure 1).
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NB3N2302
Overview
The NB3N2302 is a two−output zero delay buffer and
frequency multiplier. It provides an external feedback path
allowing maximum flexibility when implementing the Zero
Delay feature. This is explained further in the sections of this
datasheet titled “How to Implement Zero Delay,” and
“Inserting Other Devices in Feedback Path.”
Figure 3. Schematic / Suggested Layout
How to Implement Zero Delay
Inserting Other Devices in Feedback Path
Typically, Zero Delay Buffers (ZDBs) are used because a
designer wants to provide multiple copies of a clock signal
in phase with each other. The whole concept behind ZDBs
is that the signals at the destination chips are all going HIGH
at the same time as the input to the ZDB. In order to achieve
this, layout must compensate for trace length between the
ZDB and the target devices. The method of compensation is
described as follows.
External feedback is the trait that allows for this
compensation. The PLL on the ZDB causes the feedback
signal to be in phase with the reference signal. When laying
out the board, match the trace lengths between the output
being used for feedback and the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly
precede the input signal, this may also be implemented by
either making the trace to the FBIN pin a little shorter or a
little longer than the traces to the devices being clocked.
Another nice feature available due to the external
feedback is the ability to synchronize signals to the signal
coming from some other device. This implementation can
be applied to any device (ASIC, multiple output clock
buffer/driver, etc.) that is put into the feedback path.
Referring to Figure 4, if the traces between the
ASIC/Buffer and the destination of the clock signal(s) are
equal in length to the trace between the buffer and the FBIN
pin, the signals at the destination(s) device is driven HIGH
at the same time when the Reference clock provided to the
ZDB goes HIGH. Synchronizing the other outputs of the
ZDB to the outputs from the ASIC/Buffer is more complex
however, as any propagation delay from the ZDB output to
the ASIC/Buffer output must be accounted for.
Reference
Input Signal
NB3N2302
Zero
Delay
Buffer
Feedback
Signal
ASIC /
Buffer /
Fanout
Figure 4. Output Buffer in the Feedback Path
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