CMOS PARALLEL-TO-SERIAL FIFO
1,024 x 16
FEATURES:
•
•
•
•
•
•
•
•
•
IDT72125
25ns parallel port access time, 35ns cycle time
50MHz serial shift frequency
Wide x16 organization offering easy expansion
Low power consumption (50mA typical)
Least/Most Significant Bit first read selected by asserting the
FL/DIR
pin
Four memory status flags: Empty, Full, Half-Full, and Almost-
Empty/Almost-Full
Dual-Port zero fall-through architecture
Available in 28-pin 300 mil plastic DIP and 28-pin SOIC
Green parts available, see ordering information
DESCRIPTION:
The ability to buffer wide word widths (x16) make these FIFOs ideal for laser
printers, FAX machines, local area networks (LANs), video storage and disk/
tape controller applications.
Expansion in width and depth can be achieved using multiple chips. IDT’s
unique serial expansion logic makes this possible using a minimum of pins.
The unique serial output port is driven by one data pin (SO) and one clock
pin (SOCP). The Least Significant or Most Significant Bit can be read first by
programming the DIR pin after a reset.
Monitoring the FIFO is eased by the availability of four status flags: Empty,
Full, Half-Full and Almost-Empty/Almost-Full. The Full and Empty flags prevent
any FIFO data overflow or underflow conditions. The Half-Full Flag is available
in both single and expansion mode configurations. The Almost-Empty/Almost-
Full Flag is available only in a single device mode.
The IDT72125 is fabricated using submicron CMOS technology.
The IDT72125 is a high-speed, low- power, dedicated, parallel-to-serial
FIFO. This FIFO features a 16-bit parallel input port and a serial output port with
1,024 word depths, respectively.
FUNCTIONAL BLOCK DIAGRAM
RS
W
D
0
-
15
16
RESET
LOGIC
WRITE
POINTER
RAM
ARRAY
1,024 x 16
READ
POINTER
RSIX
RSOX
FL/DIR
SERIAL OUTPUT
LOGIC
EXPANSION
LOGIC
FLAG
LOGIC
FF
EF
HF
AEF
SOCP
SO
2665 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
©
2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEBRUARY 2016
DSC-2665/1
IDT72125 PARALLEL-TO-SERIAL CMOS FIFO
1,024 x 16
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
W
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
EF
FF
HF
RSIX
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
RS
SO
SOCP
RSOX/AEF
FL/DIR
2665 drw 02
PLASTIC THIN DIP (P28, order code: TP)
SOIC (SO28, order code: SO)
TOP VIEW
PIN DESCRIPTIONS
Symbol
D0–D15
RS
Reset
Name
Inputs
I/O
I
I
Data inputs for 16-bit wide data.
When
RS
is set low, internal READ and WRITE pointers are set to the first location of the RAM array.
FF
and
HF
go HIGH.
EF
and
AEF
go LOW. A reset is required before an initial WRITE after power-up.
W
must be high during the
RS
cycle. Also the First Load pin (FL) is programmed only during Reset.
A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data set-up and hold
times must be adhered to with respect to the rising edge of WRITE. Data is stored in the RAM array
sequentially and independently of any ongoing read operation.
A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In both
Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together.
This is a dual purpose input used in the width and depth expansion configurations. The First Load (FL)
function is programmed only during Reset (RS) and a LOW on
FL
indicates the first device to be loaded
with a byte of data. All other devices should be programmed HIGH. The Direction (DIR) pin controls shift
direction after Reset and tells the device whether to read out the Least Significant or Most Significant bit first.
In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain expansion, RSIX
is connected to RSOX (expansion out) of the previous device.
Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending on the
Direction pin programming. During Expansion the SO pins are tied together.
When
FF
goes LOW, the device is full and further WRITE operations are inhibited. When
FF
is HIGH,
the device is not full.
When
EF
goes LOW, the device is empty and further READ operations are inhibited. When
EF
is HIGH,
the device is not empty.
When
HF
is LOW, the device is more than half-full. When
HF
is HIGH, the device is empty to half-full.
This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an
AEF
output pin.
When
AEF
is LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When
AEF
is HIGH, the device
is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX connected to RSIX of the next device) a
pulse is sent from RSOX to RSIX to coordinate the width, depth or daisy chain expansion.
Single power supply of 5V.
Single ground of 0V.
2
Description
W
Write
I
SOCP
FL/DIR
Serial Output Clock
First Load/Direction
I
I
RSIX
SO
FF
EF
HF
RSOX/AEF
Read Serial In
Expansion
Serial Output
Full Flag
Empty Flag
Half-Full Flag
Read Serial
Out Expansion
Almost-Empty,
Almost-Full Flag
Power Supply
Ground
I
O
O
O
O
O
VCC
GND
IDT72125 PARALLEL-TO-SERIAL CMOS FIFO
1,024 x 16
COMMERCIAL TEMPERATURE RANGE
STATUS FLAGS
Number of Words in FIFO
IDT72125
0
1–127
128–512
513–896
897–1023
1024
FF
H
H
H
H
H
L
AEF
L
L
H
H
L
L
HF
H
H
H
L
L
L
EF
L
H
H
H
H
H
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
I
OUT
Description
Terminal Voltage with
Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7.0
Unit
V
°C
mA
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
(1)
T
A
Parameter
Supply Voltage
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Operating Temperature
Min.
4.5
0
2
—
0
Typ. Max. Unit
5.0
0
—
—
—
5.5
0
—
0.8
+70
V
V
V
V
°C
–55 to +125
–50 to +50
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V ± 10%, T
A
= 0
ο
C to +70
ο
C)
IDT72125
Commercial
Typ.
—
—
—
—
50
4
1
Symbol
I
LI
(1)
I
LO
(2)
V
OH
V
OL
I
CC1
(5)
I
CC2
(5,6,7)
I
CC3
(5,6,7)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic "1" Voltage IOUT = –2mA
(3)
Output Logic "0" Voltage IOUT = 8mA
(4)
Active Power Supply Current
Standby Current
(W =
RS
=
FL/DIR
= VIH; SOCP = VIL)
Power Down Current
Min.
–1
–10
2.4
—
—
—
—
Max.
1
10
—
0.4
100
8
6
Unit
μA
μA
V
V
mA
mA
mA
NOTES:
1. Measurements with 0.4V
≤
V
IN
≤
V
CC
.
2. SOCP = V
IL
, 0.4
≤
V
OUT
≤
V
CC
.
3. For SO, I
OUT
= -4mA.
4. For SO, I
OUT
= 16mA.
5. Tested with outputs open (I
OUT
= 0).
6.
RS
=
FL/DIR
=
W
= V
CC
- 0.2V; SOCP = 0.2V; all other inputs - V
CC
- 0.2.
7. Measurements are made after reset.
3
IDT72125 PARALLEL-TO-SERIAL CMOS FIFO
1,024 x 16
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V ± 10%, T
A
= 0
ο
C to +70
ο
C)
Commercial
IDT72125L25
Symbol
t
S
t
SOCP
t
WC
t
WPW
t
WR
t
DS
t
DH
t
WEF
t
WFF
t
WF
t
WPF
t
SOCP
t
SOCW
t
SOPD
t
SOHZ
t
SOLZ
t
SOCEF
t
SOCFF
t
SOCF
t
REFSO
t
RSC
t
RS
t
RSS
t
RSR
t
FLS
t
FLH
t
DIRS
t
DIRH
t
SOXD1
t
SOXD2
t
SIXS
t
SIXPW
Parameter
Parallel Shift Frequency
Serial Shift Frequency
Write Cycle Time
Write Pulse Width
Write Recovery Time
Data Set-up Time
Data Hold Time
Write High to
EF
HIGH
Write Low to
FF
LOW
Write Low to Transitioning
HF, AEF
Write Pulse Width After
FF
HIGH
Serial Clock Cycle Time
Serial Clock Width HIGH/LOW
SOCP Rising Edge to SO Valid Data
SOCP Rising Edge to SO at High-Z(1)
SOCP Rising Edge to SO at Low-Z(1)
SOCP Rising Edge to
EF
LOW
SOCP Rising Edge to
FF
HIGH
SOCP Rising Edge to Transitioning
HF, AEF
SOCP Delay After
EF
HIGH
Reset Cycle Time
Reset Pulse Width
Reset Set-up Time
Reset Recovery Time
FL
Set-up Time to
RS
Rising Edge
FL
Hold Time to
RS
Rising Edge
DIR Set-up Time to SOCP Rising Edge
DIR Hold Time from SOCP Rising Edge
SOCP Rising Edge to RSOX Rising Edge
SOCP Rising Edge to RSOX Falling Edge
RSIX Set-up Time to SOCP Rising Edge
RSIX Pulse Width
Figure
—
—
2
2
2
2
2
5, 6
4, 7
8
7
3
3
3
3
3
5, 6
4, 7
8
6
1
1
1
1
9
9
9
9
9
9
9
9
Min.
—
—
35
25
10
12
0
—
—
—
25
20
8
—
3
3
—
—
—
35
35
25
25
10
7
0
10
5
—
—
5
10
Max.
28.5
50
—
—
—
—
—
35
35
35
—
—
—
14
14
14
35
35
35
—
—
—
—
—
—
—
—
—
15
15
—
—
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARALLEL INPUT TIMINGS
SERIAL OUTPUT TIMINGS
RESET TIMINGS
EXPANSION MODE TIMINGS
NOTE:
1. Values guaranteed by design.
4
IDT72125 PARALLEL-TO-SERIAL CMOS FIFO
1,024 x 16
COMMERCIAL TEMPERATURE RANGE
5V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure A
1.1KΩ
TO
OUTPUT
PIN
680Ω
30pF
*
CAPACITANCE
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Condition
V
IN
= 0V
V
OUT
= 0V
Max.
10
12
Unit
pF
pF
or equivalent circuit
2665 drw 03
Figure A. Output Load
* Includes scope and jig capacitances.
NOTE:
1. Characterized values, not currently tested.
FUNCTIONAL DESCRIPTION
PARALLEL DATA INPUT
The device must be reset before beginning operation so that all flags are
set to their initial state. In width or depth expansion the First Load pin (FL) must
be programmed to indicate the first device.
The data is written into the FIFO in parallel through the D0–D15 input data
lines. A write cycle is initiated on the falling edge of the Write (W) signal provided
the Full Flag (FF) is not asserted. If the
W
signal changes from HIGH-to-LOW
and the Full Flag (FF) is already set, the write line is internally inhibited internally
from incrementing the write pointer and no write operation occurs.
Data set-up and hold times must be met with respect to the rising edge of Write.
On the rising edge of
W,
the write pointer is incremented. Write operations can
occur simultaneously or asynchronously with read operations.
SERIAL DATA OUTPUT
The serial data is output on the SO pin. The data is clocked out on the rising
edge of SOCP providing the Empty Flag (EF) is not asserted. If the Empty Flag
is asserted then the next data word is inhibited from moving to the output register
and being clocked out by SOCP.
The serial word is shifted out Least Significant Bit or Most Significant Bit first,
depending on the
FL/DIR
level during operation. A LOW on DIR will cause the
Least Significant Bit to be read out first. A HIGH on DIR will cause the Most
Significant Bit to be read out first.
t
RSC
t
RS
RS
t
RSS
W
t
RSC
AEF
,
EF
t
RSC
HF
,
FF
t
RSS
SOCP
NOTE 2
t
FLS
FL/DIR
NOTES:
1.
EF, FF, HF
and
AEF
may change status during Reset, but flags will be valid at t
RSC
.
2. SOCP should be in the steady LOW or HIGH during t
RSS
. The first LOW-HIGH (or HIGH-LOW) transition can begin after t
RSR
.
2665 drw 04
t
RSR
FLAG
STABLE
FLAG
STABLE
t
RSR
t
FLH
Figure 1. Reset
5
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