74AUP1G58
Low-power configurable multiple function gate
Rev. 7 — 17 September 2015
Product data sheet
1. General description
The 74AUP1G58 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XOR, inverter and buffer. All inputs can be connected to V
CC
or GND.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G58 has Schmitt trigger inputs making it capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V
T+
and the negative voltage V
T
is defined as the input
hysteresis voltage V
H
.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
Nexperia
74AUP1G58
Low-power configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AUP1G58GW
74AUP1G58GM
74AUP1G58GF
74AUP1G58GN
74AUP1G58GS
74AUP1G58GX
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SC-88
XSON6
XSON6
XSON6
XSON6
X2SON6
Description
plastic surface-mounted package; 6 leads
Version
SOT363
Type number
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
1.45
0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1
1
0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9
1.0
0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0
1.0
0.35 mm
plastic thermal extremely thin small outline package;
no leads; 6 terminals; body 1
0.8
0.35 mm
SOT1115
SOT1202
SOT1255
4. Marking
Table 2.
Marking
Marking code
[1]
aK
aK
aK
aK
aK
aK
Type number
74AUP1G58GW
74AUP1G58GM
74AUP1G58GF
74AUP1G58GN
74AUP1G58GS
74AUP1G58GX
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Fig 1.
Logic symbol
74AUP1G58
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 7 — 17 September 2015
2 of 24
Nexperia
74AUP1G58
Low-power configurable multiple function gate
6. Pinning information
6.1 Pinning
Fig 2.
Pin configuration SOT363
Fig 3.
Pin configuration SOT886
Fig 4.
Pin configuration SOT891, SOT1115 and
SOT1202
Fig 5.
Pin configuration SOT1255 (X2SON6)
6.2 Pin description
Table 3.
Symbol
B
GND
A
Y
V
CC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
74AUP1G58
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 7 — 17 September 2015
3 of 24
Nexperia
74AUP1G58
Low-power configurable multiple function gate
7. Functional description
Table 4.
Input
C
L
L
L
L
H
H
H
H
[1]
Function table
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
L
H
L
H
H
H
L
L
H = HIGH voltage level; L = LOW voltage level.
7.1 Logic configurations
Table 5.
Function selection table
Figure
see
Figure 6
see
Figure 9
see
Figure 7
and
Figure 8
see
Figure 7
and
Figure 8
see
Figure 9
see
Figure 6
see
Figure 10
see
Figure 11
see
Figure 12
Logic function
2-input NAND
2-input NAND with both inputs inverted
2-input AND with inverted input
2-input NOR with inverted input
2-input OR
2-input OR with both inputs inverted
2-input XOR
Buffer
Inverter
Fig 6.
2-input NAND gate or 2-input OR with both
inputs inverted
Fig 7.
2-input AND gate with inverted B input or
2-input NOR gate with inverted C input
74AUP1G58
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 7 — 17 September 2015
4 of 24
Nexperia
74AUP1G58
Low-power configurable multiple function gate
Fig 8.
2-input AND gate with inverted C input or
2-input NOR gate with inverted A input
Fig 9.
2-input OR gate or 2-input NAND gate with
both inputs inverted
Fig 10. 2-input XOR gate
Fig 11. Buffer
Fig 12. Inverter
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
[1]
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
50
0.5
-
-
Max
+4.6
-
+4.6
-
+4.6
20
50
Unit
V
mA
V
mA
V
mA
mA
74AUP1G58
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 7 — 17 September 2015
5 of 24
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
