74LV4053
Triple single-pole double-throw analog switch
Rev. 5 — 18 September 2014
Product data sheet
1. General description
The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use
as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device
and is pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has
a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common
input/output (nZ). All three switches share an enable input (E). A HIGH on E causes all
switches into the high-impedance OFF-state, independent of Sn.
V
CC
and GND are the supply voltage connections for the digital control inputs (Sn and E).
The V
CC
to GND range is 1 V to 6 V. The analog inputs/outputs (nY0, nY1 and nZ) can
swing between V
CC
as a positive limit and V
EE
as a negative limit. V
CC
V
EE
may not
exceed 6 V. For operation as a digital multiplexer/demultiplexer, V
EE
is connected to GND
(typically ground). V
EE
and V
SS
are the supply voltage connections for the switches.
2. Features and benefits
Optimized for low-voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Low ON resistance:
180
(typical) at V
CC
V
EE
= 2.0 V
100
(typical) at V
CC
V
EE
= 3.0 V
75
(typical) at V
CC
V
EE
= 4.5 V
Logic level translation:
To enable 3 V logic to communicate with
3
V analog signals
Typical ‘break before make’ built in
ESD protection:
HBM JESD22-A114-C exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
NXP Semiconductors
74LV4053
Triple single-pole double-throw analog switch
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV4053N
74LV4053D
74LV4053DB
74LV4053PW
74LV4053BQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
DIP16
SO16
SSOP16
TSSOP16
DHVQFN16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body
width 3.9 mm
plastic shrink small outline package; 16 leads; body
width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic dual-in line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
Version
SOT38-4
SOT109-1
SOT338-1
SOT403-1
SOT763-1
Type number
4. Functional diagram
E
6
V
CC
16
13 1Y1
S1 11
LOGIC
LEVEL
CONVERSION
DECODER
12 1Y0
14 1Z
1 2Y1
S2 10
LOGIC
LEVEL
CONVERSION
2 2Y0
15 2Z
3 3Y1
S3 9
LOGIC
LEVEL
CONVERSION
5 3Y0
4 3Z
8
GND
7
V
EE
001aak341
Fig 1.
Functional diagram
74LV4053
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 18 September 2014
2 of 27
NXP Semiconductors
74LV4053
Triple single-pole double-throw analog switch
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
Fig 4.
Schematic diagram (one switch)
74LV4053
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 18 September 2014
3 of 27
NXP Semiconductors
74LV4053
Triple single-pole double-throw analog switch
5. Pinning information
5.1 Pinning
74LV4053
2Y1
2Y0
3Y1
3Z
3Y0
E
V
EE
GND
1
2
3
4
5
6
7
8
001aak424
74LV4053
16 V
CC
15 2Z
14 1Z
13 1Y1
12 1Y0
11 S1
10 S2
9
S3
1
2
3
4
5
6
7
8
001aak342
terminal 1
index area
74LV4053
2Y1
2Y0
3Y1
3Z
3Y0
E
V
EE
GND
16 V
CC
15 2Z
14 1Z
13 1Y1
12 1Y0
11 S1
10 S2
9
S3
2Y0
3Y1
3Z
3Y0
E
V
EE
2
3
4
5
6
7
8
GND
S3
9
V
CC(1)
16 V
CC
15 2Z
14 1Z
13 1Y1
12 1Y0
11 S1
10 S2
1
2Y1
001aak343
Transparent top view
(1) This is not a supply pin. The
substrate is attached to this pad
using conductive die attach
material. There is no electrical or
mechanical requirement to
solder this pad. However, if it is
soldered, the solder land should
remain floating or be connected
to V
CC
.
Fig 5.
Pin configuration SOT38-4
and SOT109-1
Fig 6.
Pin configuration
SOT338-1 and SOT403-1
Fig 7.
Pin configuration for
SOT763-1
5.2 Pin description
Table 2.
Symbol
E
V
EE
GND
S1, S2, S3
1Y0, 2Y0, 3Y0
1Y1, 2Y1, 3Y1
1Z, 2Z, 3Z
V
CC
Pin description
Pin
6
7
8
11, 10, 9
12, 2, 5
13, 1, 3
14, 15, 4
16
Description
enable input (active LOW)
supply voltage
ground supply voltage
select input
independent input or output
independent input or output
common output or input
supply voltage
74LV4053
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 18 September 2014
4 of 27
NXP Semiconductors
74LV4053
Triple single-pole double-throw analog switch
6. Functional description
Table 3.
Inputs
E
L
L
H
[1]
Function table
[1]
Channel on
Sn
L
H
X
nY0 to nZ
nY1 to nZ
switches off
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol
V
CC
I
IK
I
SK
I
SW
T
stg
P
tot
Parameter
supply voltage
input clamping current
switch clamping current
switch current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
DIP16 package
SO16 package
TSSOP16 package
DHVQFN16 package
[1]
[3]
Conditions
[1]
Min
0.5
-
-
-
65
-
-
-
-
[2]
[2]
[2]
Max
+7.0
20
20
25
+150
750
500
500
500
Unit
V
mA
mA
mA
C
mW
mW
mW
mW
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
SW
<
0.5
V or V
SW
> V
CC
+ 0.5 V
V
SW
>
0.5
V or V
SW
< V
CC
+ 0.5 V;
source or sink current
To avoid drawing V
CC
current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no V
CC
current will flow out of terminals nYn, and in this case
there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed V
CC
or V
EE
.
The minimum input voltage rating may be exceeded if the input current rating is observed.
For DIP16 packages: above 70
C
the value of P
tot
derates linearly with 12 mW/K.
For SO16 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60
C
the value of P
tot
derates linearly with 4.5 mW/K.
[2]
[3]
74LV4053
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 18 September 2014
5 of 27
国产芯片交流
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
