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CY62126DV30L-55ZSXET

产品描述SRAM SLO 3.0V SUPER LO PWR 64K X 16 SRAM
产品类别存储   
文件大小350KB,共12页
制造商Cypress(赛普拉斯)
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CY62126DV30L-55ZSXET概述

SRAM SLO 3.0V SUPER LO PWR 64K X 16 SRAM

CY62126DV30L-55ZSXET规格参数

参数名称属性值
产品种类
Product Category
SRAM
制造商
Manufacturer
Cypress(赛普拉斯)
RoHSDetails
Memory Size1 Mbit
Organization64 k x 16
Access Time55 ns
接口类型
Interface Type
Parallel
电源电压-最大
Supply Voltage - Max
3.6 V
电源电压-最小
Supply Voltage - Min
2.2 V
Supply Current - Max10 mA
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 125 C
安装风格
Mounting Style
SMD/SMT
封装 / 箱体
Package / Case
TSOP-44
系列
Packaging
Cut Tape
系列
Packaging
Reel
系列
Packaging
MouseReel
数据速率
Data Rate
SDR
Memory TypeSDR
Number of Ports1
工作温度范围
Operating Temperature Range
- 40 C to + 125 C
工厂包装数量
Factory Pack Quantity
1000
类型
Type
Asynchronous

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CY62126DV30 MoBL
®
1-Mbit (64K x 16) Static RAM
Features
• Very high speed
— 55 ns
• Temperature Ranges
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• Wide voltage range
— 2.2V - 3.6V
• Pin compatible with CY62126BV
• Ultra-low active power
— Typical active current: 0.85 mA @ f = 1 MHz
— Typical active current: 5 mA @ f = f
Max
(55 ns speed)
• Ultra-low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 48-ball VFBGA and
44-pin TSOP Type II packages
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
HIGH). The input/output pins (I/O
0
through I/O
15
) are placed
in a high-impedance state when: deselected (CE HIGH),
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH) or during a
write operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Functional Description
[1]
The CY62126DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
64K x 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
12
A
11
A
13
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
A
14
A
15
Cypress Semiconductor Corporation
Document #: 38-05230 Rev. *H
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised July 18, 2006
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