Low Voltage, Low Skew,
1.244GHz PLL Clock Synthesizer
G
ENERAL
D
ESCRIPTION
The 843S06 is a low voltage, low skew 3.3V LVPECL Clock
Synthesizer. The device targets clock distribution in SDH/SONET
telecommunication systems but is well suited for a wide range
of applications requiring high performance high-speed clock
synthesis.
The device implements a fully integrated multiplying PLL
including:
•
An on-chip analog voltage controlled oscillator (VCO)
•
Phase-frequency detector
•
Programmable frequency dividers (prescalers)
The loop filter is external in order to optimize the PLL for different
applications.
As an option, the 843S06 may be operated with an ex-
ternal voltage controlled crystal oscillator for applications
demanding a high-Q oscillator.
843S06
DATA SHEET
F
EATURES
•
Six differential 3.3V LVPECL outputs
1,244.16/622.08MHz; 1,244.16/622.08MHz
622.08/311.04MHz;
311.04/155.52MHz
155.52/77.76MHz;
77.76/38.88MHz
•
Three selectable differential reference clock inputs
Clock frequency range: 19MHz to 622MHz
•
REF_CLKx, nREF_CLKx pairs can accept the following differ-
ential input level: LVPECL
•
Intrinsic jitter: 0.017mUI
RMS
@ 622MHz
•
Output skew: 200ps (maximum)
•
Optional external VCXO possible
•
Simple external loop filter
•
Lock detect output signal
•
Full 3.3V operating supply
•
Low power operation 0.6W (typical)
•
-40°C to 85°C ambient operating temperature
•
Lead-free (RoHS 6) packaging
V
CCA
VCTL
OCHP
SEL5
SEL4
NLDET
NLOCK
SEL3
VCXO
DCCAL
VCPSEL2
V
CC
P
IN
A
SSIGNMENT
V
EE
REF_CLK1
nREF_CLK1
V
T1
V
T2
REF_CLK2
nREF_CLK2
SEL1
V
T3
VCXO
REF_CLK3
nREF_CLK3
DCCAL VCXO
V
EE
Div.
2, 4
/2
Select
4:1
B
LOCK
D
IAGRAM
C
P
C
S
R
S
V
C
REF_CLK1:3
V
T1:3
50Ω
50Ω
CHAP
Select
3:1
VCO
2.5GHz
nREF_CLK1:3
VCOSEL1
VCOSEL2
C2
XOR
SEL1
SEL2
CHAP
NLDET
Div.
1, 2, 4, 8,
16, 32, 64
x7
Select
7:1
x7
NLOCK
x6
OEAx
FOUTx
nFOUTx
x3
SEL3:5
843S06 REVISION 11 10/23/15
1
V
CC
SEL2
OEA16
nFOUT16
FOUT16
OEA8
nFOUT8
FOUT8
OEA4
nFOUT4
FOUT4
V
CC
PFC
V
CCA
V
CC
V
EE
48 47 46 45 44 43 42 41 40 39 38 37
36
1
35
2
34
3
33
4
32
5
31
6
30
7
29
8
28
9
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS843S06
V
EE
VCOSEL1
FOUTA
nFOUTA
OEAA
FOUTB
nFOUTB
OEAB
FOUT2
nFOUT2
OEA2
V
EE
48-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm
package body
Y Package
Top View
©2015 Integrated Device Technology, Inc.
843S06 DATA SHEET
F
EATURES
The 843S06 comprises:
•
a low-noise analog VCO
•
a Phase-Frequency Detector
•
frequency dividers (prescalers)
•
a charge pump
into an integrated PLL frequency synthesizer. Careful design and
layout matching ensures short delay and minimum skew between
input reference clocks and outputs.
L
OCK
D
ETECT
The device outputs a signal NLDET that may be used to signal
whether or not the PLL is locked thus allowing fault diagnostics. The
NLDET outputs the result of an XOR operation of the signals input
to the phase-frequency detector. To be useful, this signal must be
filtered by a capacitor. The recommended value of this capacitor is
10nF. The filtered lock-detect signal is output as an LVTTL compat-
ible signal on the output NLOCK via a comparator.
PLL L
OOP
-F
ILTER
It has been chosen to locate the passive loop-filter components
externally to the device. This allows for easy optimization of the
loop-filter to different applications. The recommended loop-filter is
a simple first-order RC-Circuit as shown on
Figure 1,
resulting in a
second order, type 2 loop.
The values of R
S
, C
S
and C
P
depend on the application. With respect
to ITU-T recommended jitter performance, appropriate values for
R
S,
C
S
and C
P
have been determined to be R
S
= 3.92kΩ, C
S
= 0.22µF,
and C
P
= 1pF for input frequency of 155.52MHz; and R
S
= 9.09kΩ,
C
S
= 0.01µF, and C
P
= 0 for input frequency of 19.44MHz.
Note that the loop-filter should be terminated to the negative VCO
supply. An external VCXO might require a different termination point
for lowest point.
J
ITTER
P
ERFORMANCE
The frequency of the input reference clock may range between
19.44MHz and 622.08MHz. Since changing the reference frequency
alters the loop-gain within the PLL it may be necessary to adjust
the loop-filter components when switching to a different reference
frequency in order to achieve ITU-T recommended performance.
PLL P
ROPAGATION
D
ELAY
When the PLL is in lock, the Phase Frequency Detector aligns the
positive (low to high transition) flanks of the reference clock and
divided VCO clock on it’s inputs. These inputs are marked R and V
on
Figure 1.
This means the positive transition of any FOUTx output
clock is aligned with the positive transition of the reference clock
under the condition of equal reference clock frequency and FOUTx
output frequency, please refer to
Figure 3.
Figure 3 defines the PLL
propagation delay parameter (D
OUT
). Note that D
OUT
will change with
leakage currents drawn from the loop-filter, hence D
OUT
is loop-filter
dependant.
Figure 3 is an example for D
OUT
phase relationships. The REF_CLK[1:3]
input signals shown are in reference to FOUT2 output signals, both
running at Fx MHz with the PLL locked using the recommended
loop-filter and no excessive leakage current drawn from the charge
pump output. A skew of 200ps maximum is expected, (see Figure 4).
Skew over supply and temperature definitions are at any combination
of extremes. The expected skew values are only valid with the PLL
locked when using the recommended loop-filter. The Total Output
Uncertainty is D
OUT
+ t
skew
, (see Figures 3 and 4).
C
HARGE
P
UMP
P
OLARITY
When the PLL increases the VCO frequency, the charge pump pin
OCHP sinks current. That is, the voltage on the loop-filter capac-
itor drops to increase the oscillator frequency. So be aware, that
an external VCO must have a negative VCO constant in order to
achieve a stable lock.
O
N
-C
HIP
VCO P
OWER
D
OWN
When operated with an external VCXO the on-chip VCO should
be powered down for noise reduction. This is done by leaving V
CCA
open. See V
CCA
pin description.
NLDET
O
UTPUT
C
LOCKS
The 843S06 is equipped with six LVPECL compatible output buf-
fers. Each of the output buffers is equipped with an LVTTL enable
pin that may be used to disable clock signals not in use for noise
reduction. Clock outputs are synchronized by the falling edge. The
phases of the clock output signals are aligned with less than 200ps
skew peak-to-peak between any two clock signals. Available clock
signals from the PLL are divide by 1 (signal FOUTA and by FOUTB),
divide by 2 (FOUT2), divide by 4 (FOUT4), divide by 8 (FOUT8)
and divide by 16 (FOUT16).
F
REF
F
VAR
V
R
PFD
D
CHAP
VCO
U
C2
10nF
NLOCK
OCHP
R
S
C
S
VCTL
C
P
V
CCA
+3.3V
F
IGURE
1. A
PPLICATION
D
IAGRAM
LOW VOLTAGE, LOW SKEW,
1.244GHz PLL CLOCK SYNTHESIZER
2
REVISION 11 10/23/15
843S06 DATA SHEET
T
ABLE
1. I
NPUT
R
EFERENCE
F
REQUENCIES AS
F
UNCTION OF
SEL[3:5] S
ETTINGS
VCO Source and Corre-
sponding
VCOSEL[1:2] Settings
Internal VCO
Ext. VCO: 1244MHz
Ext. VCO: 622MHz
Internal VCO
Ext. VCO: 2488MHz
Ext. VCO: 1244MHz
0, 1
0, 0
1, 1
1, 0
0, 0
1, 1
FOUTA
MHz
622
0, 0, 0
622
N/A
1244
Input Reference Frequency (CKREFx [MHz]) and
Corresponding SEL[3:5] Settings
0, 0, 1
311
0, 1, 0
155
0, 1, 1
78
1, 0, 0
39
1, 0, 1
19
1, 1, 0
N/A
9.7
19
1, 1, 1
Disable
Feedback
1244
622
311
155
78
39
P
RESCALER
S
ETTINGS
For the PLL to achieve lock a proper relation must exist between the
input reference frequency and the setting of the on-chip prescalers.
The prescalers are set by signals: VCOSEL1, VCOSEL2, SEL3,
SEL4, and SEL5 (refer to Table 1).
First, determine the desired master output frequency. This is the fre-
quency of output clock FOUTA (FOUTA is mirrored by FOUTB). Next,
select whether the oscillator is external or internal. The VCO source
can be external (622, 1244 or 2488MHz) or internal (2488MHz).
Table 1 gives the value of VCOSEL1/2. Finally, the proper relation
between the reference clock frequency and the setting of SEL3,
SEL4, SEL5 is read from Table 1.
D
UTY
C
YCLE
C
ALIBRATION
When operated with an external oscillator, the differential LVPECL
inputs (VCXO and DCCAL) are to be used. In single-ended operation
the duty cycle of the outputs FOUTA and FOUTB may be adjusted
by tuning the voltage on DCCAL.
REVISION 11 10/23/15
3
LOW VOLTAGE, LOW SKEW,
1.244GHz PLL CLOCK SYNTHESIZER
843S06 DATA SHEET
T
ABLE
2. P
IN
D
ESCRIPTIONS
Number
1, 12,
25, 36
2
Name
V
EE
REF_CLK1
Type
Power
LVPECL IN
Description
Negative supply pins.
Non-inverting differential reference clock input.
R
T
= 50Ω termination to V
T1
.
See Figure 2, Termination of REF_CLKx. See Table 6.
Inverting differential reference clock input.
R
T
= 50Ω termination to V
T1
.
See Figure 2, Termination of REF_CLKx. See Table 6.
Termination input. Common termination point of 2 x 50Ω resistors, inter-
nally biased to 2V. Z
IN,VT1
= 1kΩ.
Termination input. Common termination point of 2 x 50Ω resistors, inter-
nally biased to 2V. Z
IN,VT2
= 1kΩ.
Non-inverting differential reference clock input.
R
T
= 50Ω termination to V
T2
.
See Figure 2, Termination of REF_CLKx. See Table 6.
Inverting differential reference clock input.
R
T
= 50Ω termination to V
T2
.
See Figure 2, Termination of REF_CLKx. See Table 6.
Pullup Reference clock select inputs. See Table 3A. LVTTL interface levels.
Note1
Termination input. Common termination point of 2 x 50Ω resistors, inter-
nally biased to 2V. Z
IN,VT3
= 1kΩ.
Non-inverting differential reference clock input.
R
T
= 50Ω termination to V
T3
.
See Figure 2, Termination of REF_CLKx. See Table 6.
Inverting differential reference clock input.
R
T
= 50Ω termination to V
T3
.
See Figure 2, Termination of REF_CLKx. See Table 6.
Core supply pins.
3
4
5
6
nREF_CLK1
V
T1
V
T2
REF_CLK2
LVPECL IN
Bias
Bias
LVPECL IN
7
nREF_CLK2
8, 14
9
10
REF_CLK3
11
nREF_CLK3
13, 24, 37
V
CC
LVPECL IN
Power
LVPECL IN
SEL1, SEL2
V
T3
LVPECL IN
LVT IN
Bias
15,
Output enable pins. When HIGH (default), the FOUTx output is enabled.
OEA16, OEA8,
18, 21
Pullup When LOW, the FOUTx output is disabled. 16kΩ resistor. LVTTL inter-
OEA4, OEA2,
LVT IN
26, 29,
Note1 face levels.
OEAB, OEAA
32
16,
nFOUT16,
Differential clock output pair (÷16). LVPECL interface levels.
LVPECL OUT
17
FOUT16
19,
nFOUT8,
Differential clock output pair (÷8). LVPECL interface levels.
LVPECL OUT
20
FOUT8
22,
nFOUT4,
Differential clock output pair (÷4). LVPECL interface levels.
LVPECL OUT
23
FOUT4
27,
nFOUT2,
Differential clock output pair (÷2). LVPECL interface levels.
LVPECL OUT
28
FOUT2
30,
nFOUTB,
Differential clock output pair (÷1). LVPECL interface levels.
LVPECL OUT
31
FOUTB
33,
nFOUTA,
Differential clock output pair (÷1). LVPECL interface levels.
LVPECL OUT
34
FOUTA
Pullup Select pins for internal or external oscillator and prescale.
35,
VCOSEL1,
LVT IN
Note1 See Table 4B. 16kΩ resistor. LVTTL interface levels.
38
VCOSEL2
NOTE 1: Pullup refers to internal pullup resistors. See Table 2, Pin Characteristics Table, for typical values.
Continued on next page.
LOW VOLTAGE, LOW SKEW,
1.244GHz PLL CLOCK SYNTHESIZER
4
REVISION 11 10/23/15
843S06 DATA SHEET
T
ABLE
2. P
IN
D
ESCRIPTIONS
,
CONTINUED
Number
Name
Type
Description
Differential external clock input, F
MAX
= 2.7GHz/1.35GHz. The input can
be used differentially or the DCCAL input may be used as a VCXO
duty cycle control. When selecting external VCXO (divide by 1) the duty
cycle of the FOUTA/B, nFOUTA/B outputs can be controlled by DCCAL.
Adjust range: 40/60 to 60/40 assuming sinusoidal input at VCXO. DC-
CAL is connected to the inverted input.
NOTE: Pins DCCAL (pin 39) and VCXO (pin 40) can handle ESD, HBM
of maximum value: 500V.
Pullup
Prescaler select inputs. See Table 4C. LVTTL interface levels.
Note1
Lock detect buffered. When 10nF is connected to NLDET, then NLOCK
= 0 signals PLL in-lock; NLOCK = 1 signals PLL out-of-lock.
See Note 2.
Lock detect unfiltered. Connect pin to a 10nF capacitor to ground.
Charge pump output to be connected to the loop filter. The pin will
sink current to increase the oscillator frequency and source current to
decrease the oscillator frequency. Refer to Figure 1.
Voltage control pin for internal VCO. To be connected to the loop filter.
39,
40
DCCAL, VCXO
LVT IN
41, 44,
45
42
43
46
47
48
SEL3, SEL4,
SEL5
NLOCK
NLDET
OCHP
VCTL
V
CCA
LVT IN
LVT OUT
Analog OUT
Analog OUT
Analog IN
Power
Internal VCO analog supply pin.
Leave open when using external VCO.
Heatsink is electrically isolated from the internal device and is attached
Heat sink
Power
facing down.
NOTE 1:
Pullup
refers to internal pullup resistors. See Table 2, Pin Characteristics Table, for typical values.
NOTE 2: Refer to the Application Note on page 15.
T
ABLE
3. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
16
Maximum
Units
pF
kΩ
REVISION 11 10/23/15
5
LOW VOLTAGE, LOW SKEW,
1.244GHz PLL CLOCK SYNTHESIZER
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