H8S/2345 Series
H8S/2345, H8S/2344, H8S/2343,
H8S/2341, H8S/2340
H8S/2345 F-ZTAT
Hardware Manual
TM
ADE-602-129A
Rev. 2.0
1/12/98
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Main Amendments and Additions in this Edition
Page
Item
Revision
Throughout • H8S/2344, H8S/2341, and H8S/2340 added; F-ZTAT version of current H8S/2345
added. Generic name adopted: H8S/2345 Series, H8S/2345 F-ZTAT Hardware
Manual.
• Notes added where necessary indicating that the H8S/2340 is a ROMless version,
and only supports MCU operating modes 1, 4, and 5.
• Notes added where necessary indicating that the H8S/2345 F-ZTAT version only
supports MCU operating modes 4 to 7, 10, 11, 14, and 15 (and that modes 1 to 3
(normal modes) cannot be used).
• Notes added where necessary indicating that the FWE pin applies only to the F-
ZTAT version, and that this pin is
WDTOVF
in the ZTAT, mask ROM, and ROMless
versions.
• Notes added where necessary indicating that the TFP-100G package is under
development.
1 to 5
9 to 13
1.1 Overview
Table 1.2 Pin Functions in Each
Operating Mode
Amended (Information on newly added
products)
Amended
• PROM mode pin names partially
changed
• Flash memory mode pin names added
14 to 20
Table 1.3 Pin Functions
Amended
• Addition of F-ZTAT version operating
mode settings by pins MD2-MD0
• FWE pin description added
69 to 72
74
76
76, 77
78
3.1 Overview
System Control Register 2 (SYSCR2) (F-
ZTAT Version Only)
3.3.7 Mode 7
3.3.8 Mode 8 to 3.3.13 Mode 15
Table 3.3 Pin Functions in Each Mode
Amended (Description of F-ZTAT and
ROMless versions added)
New
Note 2 amended
New
Amended (Mode 10, 11, 14, and 15 pin
descriptions added)
79 to 90
107
141
3.5 Memory Map in Each Operating Mode Amended (Information on newly added
products)
Table 5.3 Correspondence between
Interrupt Sources and IPR Settings
6.2.5 Bus Control Register L (BCRL)
Note amended
Description of bit 5 amended
Page
160
273
Item
Figure 6.14 Example of Wait Insertion
Timing
8.12.2 Register Configuration, Port G
Data Direction Register (PGDDR)
Revision
Amended
Description amended
Amended (Register name added to tables)
Description of bit 3 amended
Amendments to some Error column
entries (values not entered for error of 3%
or above)
294 to 309 9.2.3 Timer I/O Control Register (TIOR)
420
12.2.5 Serial Mode Register (SMR)
429 to 431 Table 12.3 BRR Settings for Various Bit
Rates (Asynchronous Mode)
441
Figure 12.2 Data Format in Asynchronous Amended
Communication (Example with 8-Bit Data,
Parity, Two Stop Bits)
Figure 12.15 Sample SCI Initialization
Flowchart
Note added
461
467
Figure 12.20 Sample Flowchart of
Note amended
Simultaneous Serial Transmit and Receive
Operations
13.2.2 Serial Status Register (SSR)
13.2.4 Serial Control Register (SCR)
Description of bits 4 and 2 amended
Description of bits 1 and 0 amended
478, 479
481
483
484
488, 489
Figure 13.2 Schematic Diagram of Smart Amended
Card Interface Pin Connections
Figure 13.3 Smart Card Interface Data
Format
Amended
Table 13.5 Examples of Bit Rate B (bit/s) Amended (ø = 20.00 MHz column added)
for Various BRR Settings (When n = 0)
Table 13.6 Examples of BRR Settings for
Bit Rate B (bit/s) (When n = 0)
491 to 493 13.3.6 Data Transfer Operations, Serial Amended
Data Transmission
497, 498
13.3.7
Operation in GSM Mode
Amended (Old section 13.3.7, Example of
Use in Software Standby Mode, replaced
with new section)
Description of bits 7 and 6 amended
(1) Amendment of setting range for analog
power supply pins etc.
(2) Deletion of module stop mode
interrupts
529
532
15.2.2 D/A Control Register (DACR)
15.4 Usage Notes
Bit 5 description amended
New
510
14.2.3
A/D Control Register (ADCR)
519 to 524 14.6 Usage Notes
Page
533
534
535
Whole of
section 17
Whole of
section 20
Item
16.1 Overview
Figure 16.1 Block Diagram of RAM
(H8S/2345, Advanced Mode)
16.3 Operation
Section 17 ROM
Revision
Description amended (Information on
newly added products)
Title of figure amended
Description amended (Information on
newly added products)
New flash memory description added, complete revision of section contents and layout
Section 20 Electrical Characteristics
Previous text used as electrical characteristics for ZTAT, mask ROM, and ROMless
versions; new F-ZTAT version electrical characteristics added.
"Preliminary" notation deleted and "TBD" replaced with values for ZTAT, mask ROM,
and ROMless versions.
666
669
675
Figure 20.9 Reset Input Timing
Figure 20.12 Basic Bus Timing (Three-
State Access)
Figure 20.24 SCK Clock Input Timing
Amended
Amended (t
WDS
specification)
Amended (t
SCKW
specification)
Amended (Replaced with latest version)
Amended (Addition of registers used by F-
ZTAT version)
Amended
• Addition of registers used by F-ZTAT
version
• Amendment of note on interrupt priority
registers A-K
677 to 752 Appendix A Instruction Set
753 to 759 B.1 Addresses
760 to 858 B.2 Functions
893
Table F.1 H8S/2345 Series Product Code Amended (Information on newly added
Lineup
products)
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