19-4813; Rev 0; 7/09
KIT
ATION
EVALU
BLE
AVAILA
1.62V to 3.6V, 8-Channel, High-Speed LLT
General Description
The MAX13055E–MAX13058E 8-channel, bidirectional
level translators provide the level shifting necessary for
100Mbps data transfer in multivoltage systems. The
MAX13055E–MAX13058E are ideal for level translation
in systems with 8 channels. Externally applied voltages,
V
CC
and V
L
, set the logic levels on either side of the
device. Logic-high signals presented on the V
L
side of
the device appear as a logic-high signal on the V
CC
side of the device and vice versa.
The MAX13055E–MAX13058E operate at full speed
with external drivers that source as little as 4mA output
current or larger. Each input/output (I/O) channel is
pulled up to V
CC
or V
L
by an internal 40µA current
source, allowing the MAX13055E–MAX13058E to be
driven by either push-pull or open-drain drivers.
The MAX13055E–MAX13058E feature an enable (EN)
input to place the device into a low-power shutdown
mode when driven low. In addition, the MAX13055E–
MAX13058E feature an automatic shutdown mode that
disables the part when V
CC
is less than V
L
. Each
device has a different I/O V
L_
and I/O V
CC_
state during
shutdown mode (see the
Ordering Information/Selector
Guide).
The MAX13055E–MAX13058E operate with V
CC
voltages
from +2.2V to +3.6V and V
L
voltages from +1.62V to
+3.2V, making them ideal for data transfer between low-
voltage ASIC/PLDs and higher voltage systems. The
MAX13055E–MAX13058E are available in 0.4mm pitch,
24-bump WLP and 28-pin TQFN (3.5mm x 5.5mm) pack-
ages. The MAX13055E–MAX13058E operate over the
extended -40°C to +85°C temperature range.
♦
100Mbps Guaranteed Data Rate
♦
8 Bidirectional Channels
♦
+1.62V
≤
V
L
≤
+3.2V and +2.2V
≤
V
CC
≤
+3.6V
Supply Voltage Range
♦
24-Bump WLP (0.4mm Pitch) Lead-Free Package
♦
28-Pin TQFN (3.5mm x 5.5mm) Lead-Free Package
♦
Extended ESD Protection on I/O V
CC
Lines
±15kV per Human Body Model
±15kV IEC 61000-4-2 Air Discharge
±8kV IEC 61000-4-2 Contact Discharge
Features
♦
Compatible with 4mA Input Drivers or Larger
MAX13055E–MAX13058E
Typical Operating Circuit
+1.8V
+3.3V
0.1μF
1μF
0.1μF
V
L
+1.8V
SYSTEM
CONTROLLER
EN
DATA
8
GND
V
CC
+3.3V
SYSTEM
MAX13055E–
MAX13058E
EN
I/O V
L_
I/O V
CC_
8
GND
DATA
GND
Applications
Low-Voltage ASIC Level
Translation
Smart Card Readers
Camera Modules
Portable POS Systems
Portable Communication
Devices
Cell Phones
GPS
Telecomm Equipment
Pin Configurations appear at end of data sheet.
Ordering Information/Selector Guide
PART
MAX13055EEWG+
MAX13055EETI+
I/O V
L
_ STATE
DURING SHUTDOWN
Open Drain
Open Drain
I/O V
CC
_ STATE
DURING SHUTDOWN
Open Drain
Open Drain
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
24 WLP
28 TQFN-EP*
Ordering Information/Selector Guide continued at end of data sheet.
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP
= Exposed pad.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
1.62V to 3.6V, 8-Channel, High-Speed LLT
MAX13055E–MAX13058E
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND.)
V
CC
, V
L .............................................................................
-0.3V to +4.0V
EN..........................................................................-0.3V to +4.0V
I/O V
CC
_ .....................................................-0.3V to (V
CC
+ 0.3V)
I/O V
L
_ ...........................................................-0.3V to (V
L
+ 0.3V)
Short-Circuit Duration
I/O to GND..................................................................Continuous
Continuous Power Dissipation (T
A
= +70°C)
28-Pin TQFN (derate 28.6mW/°C above +70°C) .......2286mW
Junction-to-Case Thermal Resistance (θ
JC
) (Note 1)
28-Pin TQFN................................................................2.7°C/W
Junction-to-Ambient Thermal Resistance (θ
JA
) (Note 1)
24-Bump WLP ..............................................................97°C/W
28-Pin TQFN.................................................................35°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to
www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +2.2V to +3.6V, V
L
= +1.62V to +3.2V, EN = V
L
, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V,
V
L
= +1.8V, and T
A
= +25°C.) (Notes 2, 3)
PARAMETER
V
L
Supply Range
V
CC
Supply Range
Supply Current from V
CC
Supply Current from V
L
V
CC
Shutdown Supply Current
V
L
Shutdown Mode Supply
Current
I/O Three-State Leakage Current
EN Input Leakage Current
V
L
- V
CC
Shutdown Threshold High
V
L
- V
CC
Shutdown Threshold Low
I/O V
CC
_ Pulldown Resistance
During Shutdown
I/O V
L
_ Pulldown Resistance
During Shutdown
I/O V
L
_ Pullup Current
(Normal Mode)
I/O V
CC
_ Pullup Current
(Normal Mode)
I/O V
L
_ to I/O V
CC
_ DC Resistance
ESD PROTECTION
All Ports
I/O V
CC
_ Only
Human Body Model
Human Body Model
IEC 61000-4-2 Air-Gap Discharge, C
VCC
= 1µF
IEC 61000-4-2 Contact Discharge, C
VCC
= 1µF
+2
+15
+15
+8
kV
kV
SYMBOL
V
L
V
CC
I
QVCC
I
QVL
I
SHDN-VCC
I
SHDN-VL
I
LEAK
I
LEAK_EN
V
TH_H
V
TH_L
I/O V
CC
_ = V
CC
, I/O V
L
_ = V
L
I/O V
CC
_ = V
CC
, I/O V
L
_ = V
L
T
A
= +25°C, EN = GND
T
A
= +25°C, EN = GND
T
A
= +25°C, EN = V
L
, V
CC
= 0V
T
A
= +25°C, EN = GND
T
A
= +25 C
V
CC
rising
V
CC
falling
0
0
10
10
20
20
3
0.1 x V
L
0.12 x V
L
16.5
16.5
o
CONDITIONS
MIN
1.62
2.2
TYP
MAX
3.2
3.6
40
10
UNITS
V
V
µA
µA
µA
µA
µA
µA
V
V
kΩ
kΩ
µA
µA
kΩ
0.1
0.1
0.1
0.1
2
1
4
2
1
0.8
0.8
23
23
65
65
R
VCC_PD_SD
MAX13056E/MAX13058E
R
VL_PD_SD
I
VL_PU_
I
VCC_PU_
R
IOVL_IOVCC
MAX13057E/MAX13058E
I/O V
L
_ = GND, I/O V
CC
_ = GND
I/O V
CC
_ = GND, I/O V
L
_ = GND
2
_______________________________________________________________________________________
1.62V to 3.6V, 8-Channel, High-Speed LLT
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +2.2V to +3.6V, V
L
= +1.62V to +3.2V, EN = V
L
, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V,
V
L
= +1.8V, and T
A
= +25°C.) (Notes 2, 3)
PARAMETER
LOGIC LEVELS
I/O V
L
_ Input-Voltage High
I/O V
L
_ Input-Voltage Low
I/O V
CC
_ Input-Voltage High
I/O V
CC
_ Input-Voltage Low
EN Input-Voltage High
EN Input-Voltage Low
I/O V
L
_ Output-Voltage High
I/O V
L
_ Output-Voltage Low
I/O V
CC
_ Output-Voltage High
I/O V
CC
_ Output-Voltage Low
V
IHL
V
ILL
V
IHC
V
ILC
V
IH
V
IL
V
OHL
V
OLL
V
OHC
V
OLC
I/O V
L_
source current = 10µA
I/O V
L_
sink current = 20µA, I/O V
CC_
< 0.1V
I/O V
CC_
source current = 10µA
I/O V
CC_
sink current = 20µA, I/O V
L_
< 0.1V
On falling edge
On rising edge
V
L
= 1.62V
V
CC
= 2.2V
V
L
= 3.2V
V
CC
= 3.6V
V
L
= 1.62V
V
CC
= 2.2V
V
L
= 3.2V
V
CC
= 3.6V
4/5
V
CC
1/5
4/5 V
L
1/5 V
L
(Note 4)
(Note 4)
(Note 4)
(Note 4)
V
L
- 0.4
0.4
V
CC
-
0.4
0.2
V
L
- 0.2
0.15
V
V
V
V
V
V
V
V
V
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX13055E–MAX13058E
RISE/FALL TIME ACCELERATOR STAGE
Accelerator Pulse Duration
V
L
Output Accelerator Source
Impedance
V
CC
Output Accelerator Source
Impedance
V
L
Output Accelerator Source
Impedance
V
CC
Output Accelerator Source
Impedance
V
L
Output Accelerator Sink
Impedance
V
CC
Output Accelerator Sink
Impedance
V
L
Output Accelerator Sink
Impedance
V
CC
Output Accelerator Sink
Impedance
3.5
24
13
11
9
14
11
10
9
ns
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
_______________________________________________________________________________________
3
1.62V to 3.6V, 8-Channel, High-Speed LLT
MAX13055E–MAX13058E
TIMING CHARACTERISTICS
(+2.2V
≤
V
CC
≤
3.6V, +1.62V
≤
V
L
≤
+3.2V; C
I/OVL_
≤
15pF, C
I/OVCC_
≤
10pF; R
SOURCE
< 150Ω, EN = V
L
, T
A
= -40°C to +85°C,
unless otherwise noted. Typical values are at VCC = +3.3V, V
L
= +1.8V, and T
A
= +25°C.) (Notes 2, 3)
PARAMETER
I/O V
CC_
Rise Time
I/O V
CC_
Fall Time
I/O V
L_
Rise Time
I/O V
L_
Fall Time
Propagation Delay
(Driving I/O V
L
_)
Propagation Delay
(Driving I/O V
CC
_)
Channel-to-Channel Skew
Propagation Delay from I/O V
L_
to I/O V
CC_
After EN
Propagation Delay from I/O V
CC_
to I/O V
L_
After EN
Maximum Data Rate
SYMBOL
t
RVCC
t
FVCC
t
RVL
t
FVL
t
PVL-VCC
t
PVCC-VL
t
SKEW
t
EN-VCC
t
EN-VL
Figure 3
Figure 3
Push-pull operation
Open drain
100
1
5
5
Figure 2
Figure 2
Figure 1
Figure 1
Figure 2
Figure 1
1
1
CONDITIONS
MIN
TYP
MAX
2.5
2.5
2.5
2.5
6.5
6.5
2
UNITS
ns
ns
ns
ns
ns
ns
ns
µs
µs
Mbps
Note 2:
All units are 100% production tested at T
A
= +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 3:
V
L
must be less than or equal to V
CC
during normal operation. However, V
L
can be greater than VCC during startup and
shutdown conditions. It will not latch up.
Note 4:
For input thresholds, see the rise/fall time accelerator circuit in Figure 4.
4
_______________________________________________________________________________________
1.62V to 3.6V, 8-Channel, High-Speed LLT
Test Circuits/Timing Diagrams
V
L
V
L
EN
MAX13055E–MAX13058E
V
L
V
CC
50%
I/O V
L_
50Ω
C
IOVCC
I/O V
CC_
I/O V
CC_
10%
10%
V
CC
I/O V
L_
50%
50%
50%
V
CC
t
RVCC
t
FVCC
MAX13055E–MAX13058E
90%
90%
t
PLH
t
PVL-VCC
= t
PLH
OR t
PHL
t
PHL
Figure 1. Push-Pull Driving I/O V
L_
Test Circuit and Timing
V
L
V
L
EN
MAX13055E–MAX13058E
V
L
V
CC
V
CC
V
CC
t
RVL
t
FVL
I/O V
CC_
50%
I/O V
L_
I/O V
CC_
50Ω
C
IOVL_
t
PLH
10%
90%
50%
50%
50%
90%
10%
I/O V
L_
t
PHL
t
PVCC-VL
= t
PLH
OR t
PHL
Figure 2. Push-Pull Driving I/O V
CC_
Test Circuit and Timing
_______________________________________________________________________________________
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
