74LVC841A
10-bit transparent latch with 5 V tolerant inputs/outputs;
3-state
Rev. 4 — 2 April 2013
Product data sheet
1. General description
The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each
latch and 3-state outputs for bus applications. A latch enable (pin LE) input and an output
enable (pin OE) input are common to all internal latches. The device consists of ten
transparent latches with 3-state true outputs. When pin LE is HIGH, data at the Dn inputs
enters the latches. In this condition, the latches are transparent, that is, a latch output
changes each time its corresponding D-input changes. When pin LE is LOW, the latches
store the information that was present at the D-inputs a set-up time preceding the HIGH to
LOW transition of pin LE.
When pin OE is LOW, the contents of the ten latches are available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the pin OE
input does not affect the state of the latches.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs/outputs; for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Flow-through pinout architecture
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C.
NXP Semiconductors
74LVC841A
10-bit transparent latch with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74LVC841AD
74LVC841ADB
74LVC841APW
74LVC841ABQ
Name
Description
plastic small outline package; 24 leads;
body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT137-1
SOT340-1
SOT355-1
Type number
40 C
to +125
C
SO24
40 C
to +125
C
SSOP24
40 C
to +125
C
TSSOP24
40 C
to +125
C
DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1
thin quad flat package; no leads; 24 terminals;
body 3.5 x 5.5 x 0.85 mm
4. Functional diagram
2
3
4
5
6
7
8
9
10
11
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Q0
Q1
Q2
Q3
Q4
23
22
21
20
19
18
17
16
15
14
LATCH
1 TO 8
3-STATE
OUTPUTS
Q5
Q6
Q7
Q8
Q9
13
1
LE
OE
001aaa842
Fig 1.
Functional diagram
74LVC841A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 2 April 2013
2 of 20
NXP Semiconductors
74LVC841A
10-bit transparent latch with 5 V tolerant inputs/outputs; 3-state
13
2
3
4
5
6
7
8
9
10
11
LE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
OE
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
23
22
21
20
19
18
17
16
15
14
2
3
4
5
6
7
8
9
10
11
13
1
C1
EN
23
22
21
20
19
18
17
16
15
14
001aaa839
1D
001aaa838
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74LVC841A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 2 April 2013
3 of 20
NXP Semiconductors
74LVC841A
10-bit transparent latch with 5 V tolerant inputs/outputs; 3-state
D0
D1
D2
D3
D4
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LE LE
LATCH
2
LE LE
LATCH
3
LE LE
LATCH
4
LE LE
LATCH
5
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
D5
D6
D7
D8
D9
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
6
LE LE
LATCH
7
LE LE
LATCH
8
LE LE
LATCH
9
LE LE
LATCH
10
LE LE
Q5
Q6
Q7
Q8
Q9
001aaa843
Fig 4.
Logic diagram
74LVC841A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 2 April 2013
4 of 20
NXP Semiconductors
74LVC841A
10-bit transparent latch with 5 V tolerant inputs/outputs; 3-state
5. Pinning information
5.1 Pinning
terminal 1
index area
D0
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 LE
001aaa836
2
3
4
5
6
7
8
9
GND
(1)
GND 12
LE 13
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
D1
D2
D3
D4
D5
D6
D7
1
OE
841
841
D8 10
D9 11
D8 10
D9 11
GND 12
001aaa837
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration for SO24 and (T)SSOP24
Fig 6.
Pin configuration for DHVQFN24
5.2 Pin description
Table 2.
Pin
1
12
13
D[0:9]
Q[0:9]
24
Pin description
Symbol
OE
GND
LE
2, 3, 4, 5, 6, 7, 8, 9, 10, 11
23, 22, 21, 20, 19, 18, 17, 16, 15, 14
V
CC
Description
output enable input (active LOW)
ground (0 V)
latch enable input (active LOW)
data input
3-state latch output
supply voltage
74LVC841A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 2 April 2013
5 of 20
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