74AUP2G241
Low-power dual buffer/line driver; 3-state
Rev. 7 — 11 February 2013
Product data sheet
1. General description
The 74AUP2G241 provides a dual non-inverting buffer/line driver with 3-state outputs.
The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH
level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. A LOW level
at pin 2OE causes output 2Y to assume a high-impedance OFF-state.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This device has an input-disable feature, which allows floating input signals. The input 1A
is disabled when the output enable input 1OE is HIGH. The input 2A is disabled when the
output enable input 2OE is LOW.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
Input-disable feature allows floating input conditions
I
OFF
circuitry provides partial Power-down mode operation
NXP Semiconductors
74AUP2G241
Low-power dual buffer/line driver; 3-state
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AUP2G241DC
74AUP2G241GT
74AUP2G241GF
74AUP2G241GD
74AUP2G241GM
74AUP2G241GN
74AUP2G241GS
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
VSSOP8
XSON8
XSON8
XSON8
XQFN8
XSON8
XSON8
Description
Version
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1
1.95
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1
0.5 mm
SOT1089
Type number
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3
2
0.5 mm
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6
1.6
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2
1.0
0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1.0
0.35 mm
SOT902-2
SOT1116
SOT1203
4. Marking
Table 2.
Marking codes
Marking code
[1]
p41
p41
p1
p41
p41
p1
p1
Type number
74AUP2G241DC
74AUP2G241GT
74AUP2G241GF
74AUP2G241GD
74AUP2G241GM
74AUP2G241GN
74AUP2G241GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74AUP2G241
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 11 February 2013
2 of 26
NXP Semiconductors
74AUP2G241
Low-power dual buffer/line driver; 3-state
5. Functional diagram
1OE
1A
2OE
2A
2Y
EN2
001aah730
001aah731
1Y
EN1
1
2
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
6. Pinning information
6.1 Pinning
74AUP2G241
1OE
1
8
V
CC
1A
2
7
2OE
74AUP2G241
2Y
1OE
1A
2Y
GND
1
2
3
4
001aaf437
3
6
1Y
8
7
6
5
V
CC
2OE
1Y
2A
GND
4
5
2A
001aaf438
Transparent top view
Fig 3.
Pin configuration SOT765-1
Fig 4.
Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74AUP2G241
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 11 February 2013
3 of 26
NXP Semiconductors
74AUP2G241
Low-power dual buffer/line driver; 3-state
74AUP2G241
terminal 1
index area
2OE
1
V
CC
8
74AUP2G241
1OE
1A
2Y
GND
1
2
3
4
8
7
6
5
V
CC
7
1OE
1Y
2OE
1Y
2A
2A
2
6
1A
3
4
5
2Y
GND
001aaf439
001aaj394
Transparent top view
Transparent top view
Fig 5.
Pin configuration SOT996-2
Fig 6.
Pin configuration SOT902-2
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203
1OE
1A, 2A
1Y, 2Y
GND
2OE
V
CC
1
2, 5
6, 3
4
7
8
SOT902-2
7
6, 3
2, 5
4
1
8
output enable input 1OE (active LOW)
data input
data output
ground (0 V)
output enable input 2OE (active HIGH)
supply voltage
Description
7. Functional description
Table 4.
Input
1OE
L
L
H
[1]
Function table
[1]
Output
1A
L
H
X
1Y
L
H
Z
Input
2OE
H
H
L
2A
L
H
X
Output
2Y
L
H
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74AUP2G241
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 11 February 2013
4 of 26
NXP Semiconductors
74AUP2G241
Low-power dual buffer/line driver; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
50
[1]
Max
+4.6
-
+4.6
-
+4.6
20
+50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
C
mW
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
0.5
-
-
50
65
T
amb
=
40 C
to +125
C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For VSSOP8 packages: above 110
C
the value of P
tot
derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118
C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 0.8 V to 3.6 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
0.8
0
0
0
40
0
Max
3.6
3.6
V
CC
3.6
+125
200
Unit
V
V
V
V
C
ns/V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= 25
C
V
IH
HIGH-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
IL
LOW-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
74AUP2G241
All information provided in this document is subject to legal disclaimers.
Conditions
Min
Typ
Max
-
-
-
-
Unit
V
V
V
V
0.70
V
CC
-
0.65
V
CC
-
1.6
2.0
-
-
-
-
-
-
-
-
-
-
0.30
V
CC
V
0.35
V
CC
V
0.7
0.9
V
V
5 of 26
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 11 February 2013
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
