74F273 Octal D-Type Flip-Flop
April 1988
Revised September 2000
74F273
Octal D-Type Flip-Flop
General Description
The 74F273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
s
Ideal buffer for MOS microprocessor or memory
s
Eight edge-triggered D-type flip-flops
s
Buffered common clock
s
Buffered, asynchronous Master Reset
s
See 74F377 for clock enable version
s
See 74F373 for transparent latch version
s
See 74F374 for 3-STATE version
Ordering Code:
Order Number
74F273SC
74F273SJ
74F273PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009511
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74F273
Unit Loading/Fan Out
U.L.
Pin Names
D
0
–D
7
MR
CP
Q
0
–Q
7
Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
Description
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
−
1 mA/20 mA
Mode Select-Function Table
Inputs
Operating Mode
MR
Reset (Clear)
Load “1”
Load “0”
L
H
H
CP
D
n
X
h
l
Q
n
L
H
L
Output
H
=
HIGH Voltage Level steady state
h
=
HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition
L
=
LOW Voltage Level steady state
I
=
LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition
X
=
Immaterial
=
LOW-to-HIGH clock transition
X
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74F273
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (min)
twice the rated I
OL
(mA)
4000V
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CCH
I
CCL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
−60
4.75
3.75
−0.6
−150
44
56
10% V
CC
5% V
CC
10% V
CC
5% V
CC
2.5
2.7
0.5
0.5
5.0
7.0
50
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
µA
µA
µA
V
µA
mA
mA
mA
Min
Min
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OL
=
20 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All other pins grounded
V
IOD
=
150 mV
All other pins grounded
V
IN
=
0.5V
V
OUT
=
0V
CP
=
D
n
=
MR
=
HIGH
3
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74F273
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Maximum Clock Frequency
Propagation Delay
Clock to Output
Propagation Delay
MR to Output
160
3.0
4.0
4.5
7.0
9.00
9.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
Max
T
A
= −55°C
to
+125°C
V
CC
=
5.0V
C
L
=
50 pF
Min
95
2.5
3.0
3.0
9.5
11.0
11.0
Max
T
A
=
0°C to
+70°C
V
CC
=
5.0V
C
L
=
50 pF
Min
130
2.5
3.5
4.0
7.5
9.0
10.0
Max
MHz
ns
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(L)
t
W
(H)
t
W
(L)
t
REC
Setup Time, HIGH or LOW
Data to CP
Hold Time, HIGH or LOW
Data to CP
MR Pulse Width, LOW
CP Pulse Width
HIGH or LOW
Recovery Time, MR to CP
3.0
3.5
0.5
1.0
6.0
6.0
6.0
3.0
Max
T
A
= −55°C
to
+125°C
V
CC
=
5.0V
Min
3.5
4.0
1.0
1.0
4.0
5.0
5.0
4.5
Max
T
A
=
0°C to
+70°C
V
CC
=
5.0V
Min
3.0
3.5
0.5
1.0
6.0
6.0
6.0
3.5
ns
ns
ns
ns
Max
Units
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4
74F273
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
5
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