MAXQ Family User’s Guide
TABLE OF CONTENTS
SECTION 1: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
SECTION 2: Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
SECTION 3: Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
SECTION 4: System Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
SECTION 5: Peripheral Register Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
SECTION 6: General-Purpose I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
SECTION 7: Timer/Counter Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
SECTION 8: Timer/Counter 1 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
SECTION 9: Timer/Counter 2 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
SECTION 10: Serial I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
SECTION 11: Serial Peripheral Interface (SPI Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
SECTION 12: Hardware Multiplier Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1
SECTION 13: 1-Wire Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1
SECTION 14: Real-Time Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1
SECTION 15: Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1
SECTION 16: In-Circuit Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1
SECTION 17: In-System Programming (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1
SECTION 18: MAXQ Family Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-1
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Rev-1
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MAXQ Family User’s Guide
SECTION 1: OVERVIEW
The MAXQ
®
family of 16-bit reduced instruction set computing (RISC) microcontrollers is targeted toward low-cost, low-power, embed-
ded-application designs. The flexible, modular architecture design used in these microcontrollers allows development of targeted
designs for specific applications with minimal effort.
Microcontrollers in the MAXQ family provide many different combinations of program memory, data memory, and peripherals while sup-
porting a common feature set. This shared functionality provides maximum reusability for hardware and software systems developed
using these microcontrollers.
1.1 Instruction Set
All MAXQ microcontrollers share a common instruction set, with all instructions a fixed 16 bits in length. A register-based, transport-
triggered architecture allows all instructions to be coded as simple transfer operations. All instructions reduce to either writing an imme-
diate value to a destination register or memory location or moving data between registers and/or memory locations.
This simple top-level instruction decoding allows all instructions to be executed in a single cycle. Since all CPU operations are per-
formed on registers only, any new functionality can be added by simply adding new register modules. The simple instruction set also
provides maximum flexibility for code optimization by a compiler.
1.2 Harvard Memory Architecture
Program memory, data memory, and register space on MAXQ microcontrollers are separate from one another, and are each accessed
by a separate bus. This type of memory architecture (known as a Harvard architecture) has some advantages.
First, the word lengths can be different for different types of memory. Program memory must be 16 bits wide to accommodate the
instruction word size, but system and peripheral registers can be 8 bits wide or 16 bits wide as needed. Since data memory is not
required to store program code, its width may also vary and could conceivably be targeted for a specific application.
Also, since data memory is accessed by the CPU only through appropriate registers, it is possible for register modules to access mem-
ory entirely independent from the main processor, providing the framework for direct memory-access operations. It is also possible to
have more than one type of data memory, each accessed through a different register set.
1.3 Register Set
Since all functions in the MAXQ family are accessed through registers, common functionality is provided through a common register
set. Many of these registers provide the equivalent of higher level op codes by directly accessing the arithmetic logic unit (ALU), the
loop counter registers, and the data pointer registers. Others, such as the interrupt registers, provide common control and configura-
tion functions that are equivalent across all MAXQ microcontrollers.
The common register set, also known as the System Registers, includes the following:
• ALU access and control registers, including working accumulator registers and the processor status flags
• Two Data Pointers and a Frame Pointer for data memory access
• Auto-decrementing Loop Counters for fast, compact looping
• Instruction Pointer and other branching control access points
• Stack Pointer and an access point to the 16-bit-wide dedicated hardware stack
• Interrupt vector, identification, and masking registers
Peripherals and other features that can vary among MAXQ microcontroller devices are accessed through Peripheral registers. These
registers, grouped into register modules, provide such additional functionality as:
• Universal Asynchronous Receiver/Transmitter (UART) Serial Ports
• High-Speed Timers and Counters
• Serial Peripheral Interface (SPI™) ports
• Hardware Multiplier
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
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MAXQ Family User’s Guide
• Real-Time Clock
• 1-Wire® Bus Master
• General-Purpose Digital I/O Ports
1.4 MAXQ10 and MAXQ20 Microcontrollers
This user’s guide covers both the 8-bit MAXQ10 and 16-bit MAXQ20 microcontrollers. The primary difference between the MAXQ10
and MAXQ20 implementations is the width of the internal data bus and ALU. The MAXQ10 design implements an 8-bit internal data
bus and ALU, while the MAXQ20 design implements a 16-bit internal data bus and ALU. This difference is most evident when com-
paring the instruction set, and more specifically, those operations that involve the ALU and accumulators. The registers on the MAXQ10
and MAXQ20 can be either 8 bits or 16 bits wide.
1-Wire is a registered trademark of Dallas Semiconductor Corp.
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