19-4314; Rev 1; 9/10
KIT
ATION
EVALU
BLE
AVAILA
Dual-Channel, 8-Bit, 65Msps ADC
General Description
Features
o
Very-Low-Power Operation (43mW/Channel at
65Msps)
o
1.8V or 2.5V to 3.3V Analog Supply
o
Excellent Dynamic Performance
49.8dBFS SNR at 70MHz
69dBc SFDR at 70MHz
o
User-Programmable Adjustments and Feature
Selection through an SPI™ Interface
o
Selectable Data Bus (Dual CMOS or Single
Multiplexed CMOS)
o
DCLK Output and Programmable Data Output
Timing Simplifies High-Speed Digital Interface
o
Very Wide Input Common-Mode Voltage Range
(0.4V to 1.4V)
o
Very High Analog Input Bandwidth (> 850MHz)
o
Single-Ended or Differential Analog Inputs
o
Single-Ended or Differential Clock Input
o
Divide-by-One (DIV1), Divide-by-Two (DIV2), and
Divide-by-Four (DIV4) Clock Modes
o
Two’s Complement, Gray Code, and Offset Binary
Output Data Format
o
Out-of-Range Indicator (DOR)
o
CMOS Output Internal Termination Options
(Programmable)
o
Reversible Bit Order (Programmable)
o
Data Output Test Patterns
o
Small, 7mm x 7mm 48-Pin Thin QFN Package with
Exposed Pad
MAX19505
The MAX19505 dual-channel, analog-to-digital convert-
er (ADC) provides 8-bit resolution and a maximum sam-
ple rate of 65Msps.
The MAX19505 analog input accepts a wide 0.4V to
1.4V input common-mode voltage range, allowing DC-
coupled inputs for a wide range of RF, IF, and base-
band front-end components. The MAX19505 provides
excellent dynamic performance from baseband to high
input frequencies beyond 400MHz, making the device
ideal for zero-intermediate frequency (ZIF) and high-
intermediate frequency (IF) sampling applications. The
typical signal-to-noise ratio (SNR) performance is
49.8dBFS and typical spurious-free dynamic range
(SFDR) is 69dBc at f
IN
= 70MHz and f
CLK
= 65MHz.
The MAX19505 operates from a 1.8V supply.
Additionally, an integrated, self-sensing voltage regula-
tor allows operation from a 2.5V to 3.3V supply (AVDD).
The digital output drivers operate on an independent
supply voltage (OVDD) over the 1.8V to 3.5V range.
The analog power consumption is only 43mW per chan-
nel at V
AVDD
= 1.8V. In addition to low operating
power, the MAX19505 consumes only 1mW in power-
down mode and 15mW in standby mode.
Various adjustments and feature selections are avail-
able through programmable registers that are
accessed through the 3-wire serial-port interface.
Alternatively, the serial-port interface can be disabled,
with the three pins available to select output mode,
data format, and clock-divider mode. Data outputs are
available through a dual parallel CMOS-compatible out-
put data bus that can also be configured as a single
multiplexed parallel CMOS bus.
The MAX19505 is available in a small 7mm x 7mm
48-pin thin QFN package and is specified over the
-40°C to +85°C extended temperature range.
Refer to the MAX19515, MAX19516, and MAX19517
data sheets for pin- and feature-compatible 10-bit,
65Msps, 100Msps, and 130Msps versions, respectively.
Refer to the MAX19506 and MAX19507 data sheets for
pin- and feature-compatible 8-bit, 100Msps and
130Msps versions, respectively.
Ordering Information
PART
MAX19505ETM+
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
48 TQFN-EP*
Applications
IF and Baseband Communications, Including
Cellular Base Stations and Point-to-Point
Microwave Receivers
Ultrasound and Medical Imaging
Portable Instrumentation and Low-Power Data
Acquisition
Digital Set-Top Boxes
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP
= Exposed pad.
Pin Configuration appears at end of data sheet.
SPI is a trademark of Motorola, Inc.
1
________________________________________________________________
Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual-Channel, 8-Bit, 65Msps ADC
MAX19505
ABSOLUTE MAXIMUM RATINGS
OVDD, AVDD to GND............................................-0.3V to +3.6V
CMA, CMB, REFIO, INA+, INA-, INB+,
INB- to GND ......................................................-0.3V to +2.1V
CLK+, CLK-, SYNC,
SPEN, CS,
SCLK, SDIN
to GND ..........-0.3V to the lower of (V
AVDD
+ 0.3V) and +3.6V
DCLKA, DCLKB, D7A–D0A, D7B–D0B, DORA, DORB
to GND..........-0.3V to the lower of (V
OVDD
+ 0.3V) and +3.6V
Continuous Power Dissipation (T
A
= +70°C)
48-Pin Thin QFN, 7mm x 7mm x 0.8mm
(derate 40mW/°C above +70°C) ................................3200mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 65MHz, A
IN
= -0.5dBFS, data output termination
= 50Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Differential Input-Voltage Range
Common-Mode Input-Voltage
Range
INL
DNL
OE
GE
V
DIFF
V
CM
f
IN
= 3MHz
f
IN
= 3MHz
Internal reference
External reference = 1.25V
Differential or single-ended inputs
(Note 2)
Fixed resistance, common mode, and
differential mode
Differential input resistance, common mode
connected to inputs
Switched capacitance common-mode input
current, each input
Fixed capacitance to ground, each input
Switched capacitance, each input
65
30
Figures 9, 10
9
0.4
> 100
kΩ
4
35
0.7
1.2
µA
pF
-0.3
-0.3
-0.4
-1.5
8
±0.0
±0.1
±0.1
±0.3
1.5
1.4
+0.3
+0.3
+0.4
+1.5
Bits
LSB
LSB
%FS
%FS
V
P-P
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS (INA+, INA-, INB+, INB-) (Figure 3)
Input Resistance
R
IN
Input Current
Input Capacitance
CONVERSION RATE
Maximum Clock Frequency
Minimum Clock Frequency
Data Latency
I
IN
C
PAR
C
SAMPLE
f
CLK
f
CLK
MHz
MHz
Cycles
2
_______________________________________________________________________________________
Dual-Channel, 8-Bit, 65Msps ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 65MHz, A
IN
= -0.5dBFS, data output termination
= 50Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
DYNAMIC PERFORMANCE
Small-Signal Noise Floor
Signal-to-Noise Ratio
SSNF
SNR
f
IN
= 70MHz, < -35dBFS
f
IN
= 3MHz
f
IN
= 70MHz
f
IN
= 175MHz
Signal-to-Noise Plus Distortion
Ratio
f
IN
= 3MHz
SINAD
f
IN
= 70MHz
f
IN
= 175MHz
Spurious-Free Dynamic Range
(2nd and 3rd Harmonic)
f
IN
= 3MHz
SFDR1
f
IN
= 70MHz
f
IN
= 175MHz
Spurious-Free Dynamic Range
(4th and Higher Harmonics)
f
IN
= 3MHz
SFDR2
f
IN
= 70MHz
f
IN
= 175MHz
f
IN
= 3MHz
Second Harmonic
HD2
f
IN
= 70MHz
f
IN
= 175MHz
f
IN
= 3MHz
Third Harmonic
HD3
f
IN
= 70MHz
f
IN
= 175MHz
f
IN
= 3MHz
Total Harmonic Distortion
THD
f
IN
= 70MHz
f
IN
= 175MHz
Third-Order Intermodulation
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
Overdrive Recovery Time
IM3
FPBW
t
AD
t
AJ
±10% beyond full scale
f
IN
= 70MHz ±1.5MHz, -7dBFS
f
IN
= 175MHz ±2.5MHz, -7dBFS
R
SOURCE
= 50Ω differential, -3dB rolloff
64.0
65.0
48.5
49.0
-49.8
49.8
49.8
49.8
49.3
49.3
49.3
77.0
77.0
77.0
69.0
69.0
69.0
-78.0
-78.0
-78.0
-82.0
-82.0
-80.0
-72.0
-72.0
-72.0
-80
-75
850
850
0.3
1
dBc
MHz
ps
ps
RMS
Cycles
-63.0
dBc
-65.0
dBc
-65.0
dBc
dBc
dBc
dB
dBFS
dBFS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX19505
_______________________________________________________________________________________
3
Dual-Channel, 8-Bit, 65Msps ADC
MAX19505
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 65MHz, A
IN
= -0.5dBFS, data output termination
= 50Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
f
INA
or f
INB
= 70MHz at -1dBFS
f
INA
or f
INB
= 175MHz at -1dBFS
f
IN
= 70MHz
f
IN
= 70MHz
f
IN
= 70MHz
V
COM
V
REFOUT
TC
REF
Default programmable setting
0.85
1.23
MIN
TYP
95
85
±0.05
±0.1
±0.5
0.9
1.25
< ±60
1.25 +5/
-10%
10
±20%
0.4 to 2.0
Self-biased
DC-coupled clock signal
Differential, default
Input Resistance
R
CLK
Differential, programmable internal
termination selected
Common mode
Input Capacitance
Single-Ended Mode Selection
Threshold (V
CLK-
)
Allowable Logic Swing (V
CLK+
)
Single-Ended Clock Input High
Threshold (V
CLK+
)
Single-Ended Clock Input Low
Threshold (V
CLK+
)
Input Leakage (CLK+)
Input Leakage (CLK-)
Input Capacitance (CLK+)
V
CLK+
= V
AVDD
= 1.8V or 3.3V
V
CLK+
= 0V
V
CLK-
= 0V
-0.5
-150
3
-50
1.5
0.3
+0.5
0 - V
AVDD
C
CLK
DC-coupled clock signal
CLOCK INPUTS (CLK+, CLK-)—SINGLE-ENDED MODE (V
CLK-
< 0.1V)
0.1
V
V
V
V
µA
µA
pF
1.20
1.0 to 1.4
10
100
9
3
0.95
1.27
MAX
UNITS
INTERCHANNEL CHARACTERISTICS
Crosstalk
Gain Match
Offset Match
Phase Match
ANALOG OUTPUTS (CMA, CMB)
CMA, CMB Output Voltage
INTERNAL REFERENCE
REFIO Output Voltage
REFIO Temperature Coefficient
EXTERNAL REFERENCE
REFIO Input-Voltage Range
REFIO Input Resistance
V
REFIN
R
REFIN
V
kΩ
V
ppm/°C
V
dBc
dB
%FSR
Degrees
CLOCK INPUTS (CLK+, CLK-)—DIFFERENTIAL MODE
Differential Clock Input Voltage
Differential Input Common-Mode
Voltage
V
P-P
V
kΩ
Ω
kΩ
pF
4
_______________________________________________________________________________________
Dual-Channel, 8-Bit, 65Msps ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 65MHz, A
IN
= -0.5dBFS, data output termination
= 50Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
CLOCK INPUT (SYNC)
Allowable Logic Swing
Sync Clock Input High Threshold
Sync Clock Input Low Threshold
Input Leakage
Input Capacitance
DIGITAL INPUTS (SHDN,
SPEN)
Allowable Logic Swing
Input High Threshold
Input Low Threshold
Input Leakage
Input Capacitance
Allowable Logic Swing
Input High Threshold
Input Low Threshold
Input Leakage
Input Capacitance
C
DIN
V
SCLK
/V
SDIN
/V
CS
= V
AVDD
= 1.8V
V
SCLK
/V
SDIN
/V
CS
= V
AVDD
= 3.3V
V
SCLK
/V
SDIN
/V
CS
= 0V, V
AVDD
= 1.8V
V
SCLK
/V
SDIN
/V
CS
= 0V, V
AVDD
= 3.3V
V
OC
V
AVDD
= 1.8V
V
AVDD
= 3.3V
I
SINK
= 200µA
I
SOURCE
= 200µA
V
OVDD
applied
GND applied
-0.5
V
OVDD
- 0.2
+0.5
7
16
-65
-105
1.35
2.58
V
SCLK
/V
SDIN
/V
CS
= V
AVDD
= 1.8V or 3.3V
V
SCLK
/V
SDIN
/V
CS
= 0V
-0.5
3
12
21
-50
-90
1.45
2.68
17
26
-35
-75
1.55
2.78
0.2
1.5
0.3
+0.5
C
DIN
V
SHDN
/V
SPEN
= V
AVDD
= 1.8V or 3.3V
V
SHDN
/V
SPEN
= 0V
-0.5
3
0 - V
AVDD
1.5
0.3
+0.5
0 - V
AVDD
V
V
V
µA
pF
V
V
V
µA
pF
V
SYNC
= V
AVDD
= 1.8V or 3.3V
V
SYNC
= 0V
-0.5
4.5
1.5
0.3
+0.5
0 - V
AVDD
V
V
V
µA
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX19505
SERIAL-PORT INPUTS (SCLK, SDIN,
CS,
where
SPEN
= 0V)—SERIAL-PORT CONTROL MODE
SERIAL-PORT INPUTS (SCLK, SDIN,
CS,
where
SPEN
= V
AVDD
)—PARALLEL CONTROL MODE (Figure 5)
Input Pullup Current
Input Pulldown Current
Open-Circuit Voltage
µA
µA
V
DIGITAL OUTPUTS (CMOS MODE, 75Ω, D0–D7 (A and B Channel), DCLKA, DCLKB, DORA, DORB)
Output-Voltage Low
Output-Voltage High
Three-State Leakage Current
V
OL
V
OH
I
LEAK
V
V
µA
_______________________________________________________________________________________
5
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