FemtoClock® Crystal-to-0.7V Differential
ICS841604I-01
DATA SHEET
General Description
The ICS841604I-01 is an optimized PCIe and sRIO clock generator.
The device uses a 25MHz parallel crystal to generate 100MHz and
125MHz clock signals, replacing solutions requiring multiple
oscillator and fanout buffer solutions. The device has excellent
phase jitter (< 1ps rms) suitable to clock components requiring
precise and low-jitter PCIe or sRIO or both clock signals. Designed
for telecom, networking and industrial applications, the
ICS841604I-01 can also drive the high-speed sRIO and PCIe
SerDes clock inputs of communication processors, DSPs, switches
and bridges.
Features
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•
•
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Four 0.7V differential HCSL outputs: configurable for PCIe
(100MHz) and sRIO (125MHz) clock signals
Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference clock
input
Supports the following output frequencies: 100MHz or 125MHz
VCO: 500MHz
PLL bypass and output enable
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.5ps (typical)
PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant
Full 3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
Q0
XTAL_IN
Pin Assignment
REF_SEL
REF_IN
V
DD
GND
XTAL_IN
XTAL_OUT
MR
V
DD
OE3
OE2
OE1
OE0
GND
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DDA
BYPASS
IREF
FSEL
V
DD
nQ3
Q3
nQ2
Q2
GND
nQ1
Q1
nQ0
Q0
OSC
XTAL_OUT
REF_IN
Pulldown
0
1
nQ0
M=
÷4
÷5
(default)
Pulldown
OE0
FemtoClock
PLL
1
VCO = 500MHz
0
Q1
nQ1
Pulldown
OE1
REF_SEL
Pulldown
M =
÷20
IREF
BYPASS
FSEL
Pulldown
Pulldown
Pulldown
OE2
Q2
nQ2
Q3
nQ3
Pulldown
OE3
MR
Pulldown
ICS841604I-01
28-Lead TSSOP, 240MIL
6.1mm x 9.7mm x 0.925
mm package body
G Package
Top View
ICS841604GI-01 REVISION A APRIL 10, 2012
1
©2012 Integrated Device Technology, Inc.
ICS841604I-01 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1
2
3, 8, 14, 24
4, 13, 19
5,
6
7
9, 10,
11, 12
15, 16
17, 18
20, 21
22, 23
25
26
Name
REF_SEL
REF_IN
V
DD
GND
XTAL_IN,
XTAL_OUT
MR
OE3, OE2,
OE1, OE0
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
FSEL
IREF
Input
Input
Power
Power
Input
Type
Pulldown
Pulldown
Description
Reference select. Selects the input reference source.
LVCMOS/LVTTL interface levels. See Table 3A.
LVCMOS/LVTTL PLL reference clock input.
Core supply pins.
Power supply ground.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input. (PLL reference.)
Pulldown
Active HIGH master reset. When logic HIGH, the internal dividers are reset.
When logic LOW, the internal dividers are enabled. See Table 3D.
LVCMOS/LVTTL interface levels.
Output enable pins. LVCMOS/LVTTL interface levels. See Table 3D.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Pulldown
Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3B.
0.7V current reference resistor output. An external fixed precision resistor (475
)
from this pin to ground provides a reference current used for differential
current-mode Qx, nQx clock outputs.
Pulldown
Selects PLL operation/PLL bypass operation. Asynchronous function.
LVCMOS/LVTTL interface levels. See Table 3C.
Analog supply pin.
Input
Input
Output
Output
Output
Output
Input
Output
Pulldown
27
28
BYPASS
V
DDA
Input
Power
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
Parameter
Input Capacitance
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
R
PULLDOWN
Input Pulldown Resistor
ICS841604GI-01 REVISION A APRIL 10, 2012
2
©2012 Integrated Device Technology, Inc.
ICS841604I-01 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR
Function Tables
Table 3A. REF_SEL Function Table
Input
REF_SEL
0
1
Input Reference
XTAL (default)
REF_IN
Table 3B. FSEL Function Table (f
REF
= 25MHz)
Inputs
FSEL
0
1
N Divider
5
4
Outputs
Q[0:3], nQ[0:3]
VCO/5 (100MHz) PCIe (default)
VCO/4 (125MHz) sRIO
Table 3C. BYPASS Function Table
Input
BYPASS
0
1
PLL Configuration
PLL enabled (default)
PLL bypassed (f
OUT
= f
REF
/N)
Table 3D. MR, OEx Function Table
Inputs
MR
OE[0:3]
OE3 = 0
OE3 = 1
OE2 = 0
0
(default)
OE2 = 1
OE1 = 0
OE1 = 1
OE0 = 0
OE0 = 1
1
X
Outputs
Q[0:3], nQ[0:3]
Q3, nQ3 are High-Impedance (default)
Q3, nQ3 are enabled
Q2, nQ2 are High-Impedance (default)
Q2, nQ2 are enabled
Q1, nQ1 are High-Impedance (default)
Q1, nQ1 are enabled
Q0, nQ0 are High-Impedance (default)
Q0, nQ0 are enabled
All outputs are High-Impedance,
all internal dividers are reset
ICS841604GI-01 REVISION A APRIL 10, 2012
3
©2012 Integrated Device Technology, Inc.
ICS841604I-01 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
64.5C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
OE[0:3] = 0
OE[0:3] = 0
Test Conditions
Minimum
3.135
V
DD
– 0.20
Typical
3.3
3.3
Maximum
3.465
V
DD
87
20
Units
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
REF_IN, REF_SEL,
BYPASS, F_SEL,
MR, OE{0:3]
REF_IN, REF_SEL,
BYPASS, F_SEL,
MR, OE{0:3]
V
DD
= V
IN
= 3.465V
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
I
IL
Input Low Current
V
DD
= 3.465V, V
IN
= 0V
-5
µA
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
ICS841604GI-01 REVISION A APRIL 10, 2012
4
©2012 Integrated Device Technology, Inc.
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Maximum
Units
pF
ICS841604I-01 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR
AC Electrical Characteristics
Table 6A. PCI Express Jitter Specifications,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
Parameter
Test Conditions
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ = 125MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ = 100MHz, 25MHz Crystal Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
ƒ = 125MHz, 25MHz Crystal Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
ƒ = 100MHz, 25MHz Crystal Input
Low Band: 10kHz - 1.5MHz
ƒ = 125MHz, 25MHz Crystal Input
Low Band: 10kHz - 1.5MHz
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ = 125MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
Minimum
Typical
12.1
Maximum
28
86
11.7
30
ps
PCIe Industry
Specification
Units
ps
t
j
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
t
REFCLK_HF_R
MS
0.82
2.15
3.1
ps
(PCIe Gen 2)
Phase Jitter RMS;
NOTE 2, 4
0.8
2.2
ps
t
REFCLK_LF_R
MS
(PCIe Gen 2)
Phase Jitter RMS;
NOTE 2, 4
0.15
0.15
0.47
3.0
0.55
ps
ps
0.17
0.41
0.8
ps
t
REFCLK_RMS
(PCIe Gen 3)
Phase Jitter RMS;
NOTE 3, 4
0.17
0.45
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the
datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen
1 is 86ps peak-to-peak for a sample size of 106 clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
ICS841604GI-01 REVISION A APRIL 10, 2012
5
©2012 Integrated Device Technology, Inc.
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