Low Skew, 1-to-4
LVCMOS-TO-LVHSTL Fanout Buffer
G
ENERAL
D
ESCRIPTION
The 8525 is a low skew, high perfor mance 1-to-4
LVCMOS-to-LVHSTL fanout buffer . The 8525 has two
selectable clock inputs thataccept LVCMOS or LVTTL
input levels and translate them to LVHSTL levels. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin.
Guaranteed output and part-to-part skew characteristics make
the 8525 ideal for those applications demanding well defined
performance and repeatability.
8525
DATA SHEET
F
EATURES
•
Four differential LVHSTL compatible outputs
•
Selectable LVCMOS / LVTTL clock inputs for redundant
and multiple frequency fanout applications
•
Maximum output frequency: 266MHz
•
Translates LVCMOS and LVTTL levels to LVHSTL levels
•
Output skew: 35ps (maximum)
•
Part-to-part skew: 150ps (maximum)
•
Propagation delay: 1.9ns (maximum)
•
3.3V core, 1.8V operating supply
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
•
Available in lead-free RoHS compliant packages
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
8525
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
8525 REVISION D 7/8/14
1
©2015 Integrated Device Technology, Inc.
8525 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
6
5, 7, 8, 9
10
13, 18
11, 12
14, 15
16, 17
19, 20
Name
GND
CLK_EN
CLK_SEL
CLK0
CLK1
nc
V
DD
V
DDO
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Power
Input
Input
Input
Input
Unused
Power
Power
Output
Output
Output
Output
Type
Description
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
Pullup
When LOW, Q outputs are forced low, nQ outputs are forced high. LVC-
MOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK1 input.
Pulldown
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
Pulldown LVCMOS / LVTTL clock input.
Pulldown LVCMOS / LVTTL clock input.
No connect.
Positive supply pin.
Output supply pins.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
LOW SKEW, 1-TO-4
LVCMOS-TO-LVHSTL FANOUT BUFFER
2
REVISION D 7/8/15
8525 DATA SHEET
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_EN
0
0
1
CLK_SEL
0
1
0
Selected Source
CLK0
CLK1
CLK0
Q0:Q3
Disabled; LOW
Disabled; LOW
Enabled
Outputs
nQ0:nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
1
1
CLK1
Enabled
Enabled
After CLK_EN switches, the clock ooutputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B.
F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK0 or CLK1
0
1
Q0:Q3
LOW
HIGH
Outputs
nQ0:nQ3
HIGH
LOW
REVISION D 7/8/15
3
LOW SKEW, 1-TO-4
LVCMOS-TO-LVHSTL FANOUT BUFFER
8525 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only.
Functional operation of product at these conditions or any
conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
50
Units
V
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
V
IH
Parameter
CLK0, CLK1
Input High Voltage
CLK_EN, CLK_
SEL
CLK0, CLK1
V
IL
Input Low Voltage
CLK_EN, CLK_
SEL
CLK0, CLK1,
CLK_SEL
CLK_EN
I
IL
Input Low Current
CLK0, CLK1,
CLK_SEL
CLK_EN
Test Conditions
Minimum
2
2
-0.3
-0.3
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Typical
Maximum
3.765
3.765
1.3
0.8
150
5
Units
V
V
V
V
µA
µA
µA
µA
I
IH
Input High Current
T
ABLE
4C. LVHSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
OX
V
SWING
Parameter
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
Output Crossover Voltage
Peak-to-Peak
Output Voltage Swing
Test Conditions
Minimum
1
0
40% x (V
OH
-V
OL
) + V
OL
0.75
Typical
Maximum
1.2
0.4
60% x (V
OH
-V
OL
) + V
OL
1.25
Units
V
V
V
V
NOTE 1: Outputs terminated with 50Ω to GND.
LOW SKEW, 1-TO-4
LVCMOS-TO-LVHSTL FANOUT BUFFER
4
REVISION D 7/8/15
8525 DATA SHEET
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
t
R /
t
F
odc
Parameter
Maximum Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80% @ 50MHz
300
45
50
ƒ
≤
266MHz
1.0
Test Conditions
Minimum
Typical
Maximum
266
1.9
35
150
700
55
Units
MHz
ns
ps
ps
ps
%
All parameters measured at 266MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
REVISION D 7/8/15
5
LOW SKEW, 1-TO-4
LVCMOS-TO-LVHSTL FANOUT BUFFER
TI技术论坛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
