74ABT648
Octal transceiver/register; inverting; 3-state
Rev. 04 — 27 April 2005
Product data sheet
1. General description
The 74ABT648 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT648 transceiver/register consists of bus transceiver circuits with inverting
3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or the internal registers. Data on the A or B
bus will be clocked into the registers as the appropriate clock pin goes HIGH.
Output enable (OE) and direction (DIR) pins are provided to control the transceiver
function.
In the transceiver mode, data present at the high-impedance port may be stored in either
the A or B register or both.
The select (SAB, SBA) pins determine whether data is stored or transferred through the
device in real time. The DIR determines which bus will receive data when the OE is active
(LOW).
In the isolation mode (OE = HIGH), data from bus A may be stored in the B register and/or
data from bus B may be stored in the A register. Outputs from real time or stored registers
will be inverted. When an output function is disabled, the input function is still enabled and
may be used to store and transmit data. Only one of the two buses A or B may be driven
at a time.
2. Features
s
s
s
s
s
s
s
s
s
Combines 74ABT245 and 74ABT374A type functions in one device
Independent registers for A and B buses
Multiplexed real time and stored data
3-state buffers
Live insertion and extraction permitted
Output capability: +64 mA and
−32
mA
Power-up 3-state
Power-up reset
Latch-up protection:
x
JESD78: exceeds 500 mA
s
ESD protection:
x
MIL STD 883 method 3015: exceeds 2000 V
x
Machine model: exceeds 200 V
Philips Semiconductors
74ABT648
Octal transceiver/register; inverting; 3-state
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C.
Symbol Parameter
t
PLH
t
PHL
C
I
C
I/O
I
CC
propagation delay An to Bn or
Bn to An
propagation delay An to Bn or
Bn to An
input capacitance on pins CP, S,
OE, DIR
I/O capacitance
quiescent supply current
Conditions
C
L
= 50 pF; V
CC
= 5 V
C
L
= 50 pF; V
CC
= 5 V
V
I
= 0 V or V
CC
outputs disabled;
V
O
= 0 V or V
CC
outputs 3-state;
V
CC
= 5.5 V
Min
-
-
-
-
-
Typ Max
3.3
3.4
4
7
-
-
-
-
Unit
ns
ns
pF
pF
µA
110 -
4. Ordering information
Table 2:
Ordering information
Package
Temperature range
74ABT648D
74ABT648PW
−40 °C
to +85
°C
−40 °C
to +85
°C
Name
SO24
TSSOP24
Description
plastic small outline package;
24 leads; bodywidth 7.5 mm
plastic thin shrink small outline package;
24 leads; body width 4.4 mm
Version
SOT137-1
SOT355-1
Type number
5. Functional diagram
21
3
22
2
23
1
4
1
2
3
23
22
21
A0 A1 A2 A3 A4 A5 A6 A7
CPAB
SAB
DIR
CPBA
SBA
OE
B0 B1 B2 B3 B4 B5 B6 B7
20 19 18 17 16 15 14 13
001aac744
4
5
6
7
8
9
10 11
G3
3EN1[BA]
3EN2[AB]
G6
G7
C4
C5
1
1
5D 7
6
4D
1
2
19
18
17
16
15
14
13
001aac745
20
6 1
5
6
7
8
9
10
11
1 7
Fig 1. Logic symbol
Fig 2. IEC logic symbol
9397 750 14858
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 27 April 2005
2 of 19
Philips Semiconductors
74ABT648
Octal transceiver/register; inverting; 3-state
OE
21
DIR
CPBA
SBA
CPAB
SAB
3
23
22
1
2
1 OF 8 CHANNELS
1D
C1
Q
A0
4
1D
C1
Q
20
B0
A1
A2
A3
A4
A5
A6
A7
5
6
7
8
9
10
11
OTHER CHANNELS
19
18
17
16
15
14
13
001aac747
B1
B2
B3
B4
B5
B6
B7
Fig 3. Logic diagram
9397 750 14858
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 27 April 2005
3 of 19
Philips Semiconductors
74ABT648
Octal transceiver/register; inverting; 3-state
6. Pinning information
6.1 Pinning
CPAB
SAB
DIR
A0
A1
A2
A3
A4
A5
1
2
3
4
5
6
7
8
9
24 V
CC
23 CPBA
22 SBA
21 OE
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
001aac743
648
A6 10
A7 11
GND 12
Fig 4. Pin configuration
6.2 Pin description
Table 3:
Symbol
CPAB
SAB
DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
B7
B6
B5
B4
B3
B2
B1
B0
OE
9397 750 14858
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Description
A to B clock input
A to B select input
direction control input
data input/output 0 (A side)
data input/output 1 (A side)
data input/output 2 (A side)
data input/output 3 (A side)
data input/output 4 (A side)
data input/output 5 (A side)
data input/output 6 (A side)
data input/output 7 (A side)
ground (0 V)
data input/output 7 (B side)
data input/output 6 (B side)
data input/output 5 (B side)
data input/output 4 (B side)
data input/output 3 (B side)
data input/output 2 (B side)
data input/output 1 (B side)
data input/output 0 (B side)
output enable input (active LOW)
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 27 April 2005
4 of 19
Philips Semiconductors
74ABT648
Octal transceiver/register; inverting; 3-state
Pin description
…continued
Pin
22
23
24
Description
B to A select input
B to A clock input
supply voltage
Table 3:
Symbol
SBA
CPBA
V
CC
7. Functional description
7.1 Function table
Table 4:
Function table
[1]
Input
OE
Store A or B
Store A, B unspecified
Store B, A unspecified
Store A and B
Store A and B data
Isolation, hold storage
B data to A bus
Real time B data to A bus
Stored B data to A bus
A data to B bus
Real time A data to B bus
Stored A data to B bus
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑
= LOW-to-HIGH clock transition.
[2]
The data output function may be enabled or disabled by various signals at the OE input. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition of the clock.
Operating mode
Data I/O
DIR
X
X
CPAB
↑
X
CPBA
X
↑
SAB
X
X
SBA
X
X
An
input
unspecified
output
[2]
input
Bn
unspecified
output
[2]
input
X
X
H
H
L
L
L
L
X
X
L
L
H
H
↑
H or L
X
X
X
H or L
↑
H or L
X
H or L
X
X
X
X
X
X
L
H
X
X
L
H
X
X
input
output
input
input
output
9397 750 14858
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 27 April 2005
5 of 19
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
