MGA-638P8
High Linearity Low Noise Amplifier
Data Sheet
Description
Avago Technologies’ MGA-638P8 is an economical, easy-
to-use GaAs MMIC Low Noise Amplifier (LNA). This LNA
has low noise and high linearity achieved through the
use of Avago Technologies’ proprietary 0.25
m
GaAs
Enhancement-mode pHEMT process. It is housed in the
miniature 2.0 x 2.0 x 0.75 mm
3
8-pin Dual-Flat-Non-Lead
(DFN) package. The device is designed for optimum use
from 2.5 GHz up to 4.0 GHz. The compact footprint and
low profile coupled with low noise, high gain and high
linearity make this an ideal choice as a low noise amplifier
for cellular infrastructure applications such as LTE, GSM,
CDMA, W-CDMA, CDMA2000 & TD-SCDMA. For optimum
performance at lower frequency from 450 MHz up to 1.5
GHz, MGA-636P8 is recommended. For optimum perfor-
mance from 1.5 GHz up to 2.5 GHz, MGA-637P8 is recom-
mended. All these 3 products, MGA-636P8, MGA-637P8
and MGA-638P8 share the same package and pinout con-
figuration.
Features
High linearity performance.
Low Noise Figure.
GaAs E-pHEMT Technology
[1].
Low cost small package size.
Integrated with active bias and option to access FET
gate.
Integrated power down control pin.
Specifications
2.5 GHz; 4.8 V, 84 mA
17.3 dB Gain
0.87 dB Noise Figure
14 dB Input Return Loss
22.6
dBm Input IP3
22.2
dBm Output Power at 1 dB gain compression
Pin Configuration and Package Marking
2.0 x 2.0 x 0.75 mm
3
8-lead DFN
[1]
[2]
[3]
[4]
TOP VIEW
Pin 1 – Not Used
Pin 2 – RFinput
Pin 3 – Vbias2
Pin 4 – Not Used
Center paddle – GND
[8]
[7]
[6]
[5]
[8]
[7]
[6]
[5]
GND
[1]
[2]
[3]
[4]
Applications
Cellular infrastructure applications such as LTE, GSM,
CDMA, W-CDMA, CDMA2000 & TD-SCDMA.
Other low noise applications.
Note:
1. Enhancement mode technology employs positive Vgs, thereby
eliminating the need of negative gate voltage associated with con-
ventional depletion mode devices.
38X
BOTTOM VIEW
Pin 5 – Vbias1
Pin 6 – PwrDwn
Pin 7 – RFoutput
Pin 8 – Not Used
Note:
Package marking provides orientation and identification
“38” = Product Code
“X” = Month Code
It is recommended to ground Pin1, 4 and 8 which are Not Used.
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 100 V
ESD Human Body Model = 350 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Simplified Schematic
[1]
Vdd
C6
R2
C4
L3
RFin
C1
[1]
[NU]
[2]
[RFinput]
[3]
[Vbias2]
[4]
[NU]
Bias
[8]
[NU]
[7]
[RFoutput]
[6]
[PwrDwn]
[5]
[Vbias1]
L2
C2
RFout
L1
C3
R1
Rb
C5
Vbias1
C7
C8
PwrDwn
Note:
1. Device is turned ON when PwrDwn pin is applied with 0 V or left
open. Device is turned OFF when PwrDwn pin is applied with 3.3 V
Absolute Maximum Rating
[1]
T
A
=25° C
Symbol
V
dd
I
dd
Vbias1
V
pwrDwn
P
in,max
P
diss
T
j
T
STG
Thermal Resistance
Units
V
mA
V
V
dBm
W
°C
°C
Parameter
Device Voltage,
RF output to ground
Drain Current
Bias Voltage
Power Down Voltage
CW RF Input Power
Total Power Dissipation
Junction Temperature
Storage Temperature
Absolute Maximum
5.5
125
5.5
5.5
+24
0.61
150
-65 to 150
Thermal Resistance
[2]
(V
dd
= 4.8 V, I
dd
= 84 mA)
jc
= 67°C/W
Notes:
1. Operation of this device in excess of any of
these limits may cause permanent damage.
2. Thermal resistance measured using Infra-Red
Measurement Technique.
3. Power dissipation with unit turned on. Board
temperature T
C
is 25° C. Derate at 14.9 mW/°C
for T
c
> 105.8° C.
2
Electrical Specifications
[1,4]
T
A
= 25° C, Vdd = Vbias1 = 4.8 V, RF measurement at 2.5 GHz, measured on demo board in Figure 5 with component listed
in Table1.
Symbol
Idd
I
PwrDwn
Gain
NF
[2]
IIP3
[3]
OP1dB
IRL
ORL
Parameter and Test Condition
Bias Current
Current at V
PwrDwn
pin when V
PwrDwn
= 3.3 V
(Power Down mode)
Gain
Noise Figure
Input Third Order Intercept Point
Output Power at 1dB Gain Compression
Input Return Loss, 50
source
Output Return Loss, 50
load
Units
mA
mA
dB
dB
dBm
dBm
dB
dB
Min.
60
–
16
–
21
–
–
–
Typ.
84
0.15
17.3
0.87
22.6
22.2
14
10
Max.
110
–
19
1.15
–
–
–
–
Notes:
1. Measurements at 2.5 GHz obtained using demo board described in Figure 5.
2. For NF data, board losses of the input have not been de-embedded.
3. IIP3 test condition: F
RF1
= 2.500 GHz, F
RF2
= 2.501 GHz with input power of -10 dBm per tone.
4. Use proper bias, heatsink and derating to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and application
note for more details.
Product Consistency Distribution Charts
[1, 2]
LSL
USL
USL
50
60
70
80
90
100
110
0.7
0.8
0.9
1
1.1
1.2
Figure 1. Idd, LSL = 60 mA , nominal = 84 mA, USL = 110 mA
Figure 2. NF, nominal = 0.87 dB, USL = 1.15 dB
LSL
LSL
USL
20
21
22
23
24
25
16
17
18
19
Figure 3. IIP3, LSL = 21 dBm, nominal = 22.6 dBm
Figure 4. Gain, LSL = 16 dB, nominal = 17.3 dB, USL = 19 dB
Notes:
1. Distribution data sample size is 500 samples taken from 3 different wafer lots. Future wafers allocated to this product may have nominal values
anywhere between the upper and lower limits.
2. Circuit trace losses have not been de-embedded from measurements above.
3
Demo Board Layout
Avago
Technologies
BTS LNA
Nov 2010
Demo Board Schematic
Vdd
C6
R2
RFin
L3
C1
L1
C3
Rb
R1
C5
C7
C8
C2
L2
C4
C6
C4
RFout
L3
RFin
C1
[1]
[NU]
[2]
[RFinput]
[3]
[Vbias2]
[4]
[NU]
Bias
[8]
[NU]
[7]
[RFoutput]
[6]
[PwrDwn]
[5]
[Vbias1]
L2
C2
RFout
L1
C3
R1
Rb
C5
C7
Vbias1
C8
PwrDwn
PwrDwn
Vbias1
Vdd
Figure 5. Demo Board Layout Diagram
Truth Table
V
PwrDwn
(V)
LNA Mode
Power Down Mode
0 or open
3.3
– Recommended PCB material is 10 mils Rogers RO4350.
– Suggested component values may vary according to
layout and PCB material.
Figure 6. Demo Board Schematic Diagram
Notes:
The schematic is shown with the assumption that similar PCB is used
for all MGA-636P8, MGA-637P8 and MGA-638P8.
Detail of the components needed for this product is shown in Table 1.
Table 1. Component list for 2.5 GHz matching
Part
C1
C2
C5, C6, C7, C8
C3, C4
L1
L2
L3
Rb
R1
R2
Notes:
C1, C2 are DC blocking capacitors
C1, L1, L3 input match for NF
L2 output match for IP3
C5, C6, C7, C8 are bypass capacitors
R1 is a stabilizing resistor
Rb is the biasing resistor
Size
0402
0402
0603
0402
0402
0402
0402
0402
0402
0402
Value
1.8 pF (Murata)
100 pF (Murata)
4.7
F
(Murata)
Not Used
8.2 nH (Toko)
5.6 nH (Toko)
1.8 nH (Toko)
680 ohm (Rohm)
51 ohm (Rohm)
0 ohm (Rohm)
Detail Part Number
GRM1555C1H1R8CB01D
GRM1555C1H101JD01D
GRM188R60J475KE19D
LLP1005-FH8N2C
LLP1005-FH5N6C
LLP1005-FH1N8C
MCR004YZPJ680
MCR004YZPJ510
MCR01MZPJ000
4
Typical Performance
RF performance at T
A
= 25° C, Vdd = 4.8 V, Idd = 84 mA, measured using 50 ohm input and output board unless stated
otherwise. IIP3 test condition: F
RF1
-F
RF2
= 1 MHz with input power of -10 dBm per tone.
0.9
0.8
0.7
Fmin (dB)
Fmin (dB)
0.6
0.5
0.4
0.3
60
80
84
Idd (mA)
90
100
0.9
0.8
0.7
0.6
0.5
0.4
0.3
60
80
84
Idd (mA)
90
100
Figure 7. Fmin vs Idd at 4.8 V at 2.5 GHz
Figure 8. Fmin vs Idd at 4.8 V at 2 GHz
22
20
18
16
14
12
10
8
6
4
2
0
60
80
84
Idd (mA)
90
100
22
20
18
16
14
12
10
8
6
4
2
0
Gain(dB)
Gain(dB)
60
80
84
Idd (mA)
90
100
Figure 9. Gain vs Idd at 4.8 V Tuned for Optimum IIP3 and Fmin at 2.5 GHz
Figure 10. Gain vs Idd at 4.8 V Tuned for Optimum IIP3 and Fmin at 2 GHz
35
30
25
IIP3 (dBm)
IIP3 (dBm)
20
15
10
5
0
60
80
84
Idd (mA)
90
100
35
30
25
20
15
10
5
0
60
80
84
Idd (mA)
90
100
Figure 11. IIP3 vs Idd at 4.8 V Tuned for Optimum IIP3 and Fmin at 2.5 GHz
Figure 12. IIP3 vs Idd at 4.8 V Tuned for Optimum IIP3 and Fmin at 2 GHz
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