VIPer01
Energy saving off-line high voltage converter
Datasheet - production data
Figure 1: Basic application schematic
Jittered switching frequency reduces the
EMI filter cost:
30 kHz ± 7% (type X)
60 kHz ± 7% (type L)
120 kHz ± 7% (type H)
Embedded E/A with 1.2 V reference
Protections with automatic restart:
overload/short-circuit (OLP), line or output
OVP, max. duty cycle counter, V
CC
clamp
Pulse-skip protection to prevent
flux-runaway
Embedded thermal shutdown
Built-in soft-start for improved system
reliability
Applications
Low power SMPS for home appliances,
building and home control, small industrial,
consumers, lighting, motion control
Low power adapters
Description
Features
800 V avalanche-rugged power MOSFET
allowing ultra wide V
AC
input range to be
covered
Embedded HV startup and sense-FET
Current mode PWM controller
Drain current limit protection (OCP)
Wide supply voltage range: 4.5 V to 30 V
Self-supply option allows the auxiliary
winding or bias components to be removed
Minimized system input power consumption:
Less than 10 mW @ 230 V
AC
in no-load
condition
Less than 400 mW @ 230 V
AC
with
250 mW load
The device is a high voltage converter smartly
integrating an 800 V avalanche-rugged power
MOSFET with PWM current mode control. The
power MOSFET with 800 V breakdown voltage
allows the extended input voltage range to be
applied, as well as the size of the DRAIN snubber
circuit to be reduced. This IC meets the most
stringent energy-saving standards as it has very
low consumption and operates in pulse frequency
modulation under light load. The design of
flyback, buck and buck boost converters is
supported. The integrated HV startup, sense-
FET, error amplifier and oscillator with jitter allow
a complete application to be designed with the
minimum number of components.
March 2016
DocID028751 Rev 1
1/36
www.st.com
This is information on a product in full production.
Contents
VIPer01
Contents
1
2
3
4
Pin setting ........................................................................................ 5
Electrical and thermal ratings ........................................................ 6
2.1
Electrical characteristics .................................................................... 8
Typical electrical characteristics.................................................. 12
General description ....................................................................... 16
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
Block diagram ................................................................................. 16
Typical power capability .................................................................. 16
Primary MOSFET ............................................................................ 17
High voltage startup ........................................................................ 17
Soft-start ......................................................................................... 19
Oscillator ......................................................................................... 19
Pulse-skipping ................................................................................. 19
Direct feedback ............................................................................... 21
Secondary feedback ....................................................................... 21
Pulse frequency modulation ............................................................ 21
Overload protection ......................................................................... 22
Max. duty cycle counter protection .................................................. 22
VCC clamp protection ..................................................................... 23
Disable function............................................................................... 23
Thermal shutdown ........................................................................... 25
Typical schematics .......................................................................... 26
Energy saving performance ............................................................ 29
Layout guidelines and design recommendations ............................ 30
SSOP10 package information ......................................................... 32
5
Application information ................................................................ 26
5.1
5.3
5.4
6
7
8
Package information ..................................................................... 32
6.1
Ordering information..................................................................... 34
Revision history ............................................................................ 35
2/36
DocID028751 Rev 1
VIPer01
List of tables
List of tables
Table 1: Pin description .............................................................................................................................. 5
Table 2: Absolute maximum ratings ........................................................................................................... 6
Table 3: Thermal data ................................................................................................................................. 6
Table 4: Avalanche characteristics ............................................................................................................. 7
Table 5: Power section ............................................................................................................................... 8
Table 6: Supply section............................................................................................................................... 8
Table 7: Controller section .......................................................................................................................... 9
Table 8: Typical power .............................................................................................................................. 16
Table 9: Power supply efficiency, V
OUT
= 5 V ........................................................................................... 29
Table 10: SSOP10 mechanical data ......................................................................................................... 33
Table 11: Order code ................................................................................................................................ 34
Table 12: Document revision history ........................................................................................................ 35
DocID028751 Rev 1
3/36
List of figures
VIPer01
List of figures
Figure 1: Basic application schematic ........................................................................................................ 1
Figure 2: Connection diagram .................................................................................................................... 5
Figure 3: R
thJA
/(R
thJA
@A=100 mm²) ............................................................................................................ 7
Figure 4: I
DLIM
vs T
J
................................................................................................................................... 12
Figure 5: F
OSC
vs T
J
................................................................................................................................... 12
Figure 6: V
HV_START
vs T
J
........................................................................................................................... 12
Figure 7: V
FB_REF
vs T
J
.............................................................................................................................. 12
Figure 8: Quiescent current Iq vs T
J
......................................................................................................... 12
Figure 9: Operating current I
CC
vs T
J
........................................................................................................ 12
Figure 10: I
CH1
vs T
J
.................................................................................................................................. 13
Figure 11: I
CH1
vs V
DRAIN
............................................................................................................................ 13
Figure 12: I
CH2
vs T
J
.................................................................................................................................. 13
Figure 13: I
CH2
vs V
DRAIN
............................................................................................................................ 13
Figure 14: I
CH3
vs T
J
.................................................................................................................................. 13
Figure 15: I
CH3
vs V
DRAIN
............................................................................................................................ 13
Figure 16: G
M
vs T
J
................................................................................................................................... 14
Figure 17: I
COMP
vs T
J
................................................................................................................................ 14
Figure 18: R
DS(on)
vs T
J
.............................................................................................................................. 14
Figure 19: Static drain-source on-resistance ............................................................................................ 14
Figure 20: V
BVDSS
vs T
J
............................................................................................................................. 14
Figure 21: Output characteristic ................................................................................................................ 14
Figure 22: SOA SSOP10 package ........................................................................................................... 15
Figure 23: Maximum avalanche energy vs T
J
........................................................................................... 15
Figure 24: Block diagram .......................................................................................................................... 16
Figure 25: IC supply modes: self-supply and external supply .................................................................. 17
Figure 26: Power-ON and power-OFF...................................................................................................... 18
Figure 27: Soft startup .............................................................................................................................. 19
Figure 28: Pulse-skipping during startup .................................................................................................. 20
Figure 29: Short-circuit condition .............................................................................................................. 22
Figure 30: Connection for input overvoltage protection (isolated or non-isolated topologies) ................. 23
Figure 31: Connection for output overvoltage protection (non-isolated topologies) ................................. 24
Figure 32: Thermal shutdown timing diagram .......................................................................................... 25
Figure 33: Flyback converter (non-isolated) ............................................................................................. 26
Figure 34: Flyback converter with line OVP (non-isolated) ...................................................................... 26
Figure 35: Flyback converter (isolated) .................................................................................................... 27
Figure 36: Primary side regulation isolated flyback converter .................................................................. 27
Figure 37: Buck converter (positive output) .............................................................................................. 28
Figure 38: Buck-boost converter (negative output) .................................................................................. 28
Figure 39: P
IN
versus V
IN
in no-load, V
OUT
= 5 V ....................................................................................... 29
Figure 40: P
IN
versus V
IN
in light load, V
OUT
= 5 V .................................................................................... 29
Figure 41: Recommended routing for flyback converter ........................................................................... 31
Figure 42: Recommended routing for buck converter .............................................................................. 31
Figure 43: SSOP10 package outline ........................................................................................................ 32
Figure 44: SSOP10 recommended footprint............................................................................................. 33
4/36
DocID028751 Rev 1
VIPer01
Pin setting
1
Pin setting
Figure 2: Connection diagram
Table 1: Pin description
SSOP10
Name
Function
Ground and MOSFET source.
Connection of source of the internal MOSFET
and the return of the bias current of the device. All groundings of bias
components must be tied to a trace going to this pin and kept separate from the
pulsed current return.
Controller supply.
An external storage capacitor has to be connected across
this pin and GND. The pin, internally connected to the high voltage current
source, provides the VCC capacitor charging current at startup and during
steady-state operation, if the self-supply mode is selected. A small bypass
capacitor (0.1 μF typ.) in parallel, placed as close as possible to the IC, is also
recommended, for noise filtering purpose.
Disable.
If its voltage exceeds the internal threshold V
DIS_th
(1.2 V typ.) for more
than t
DEB
time (1 ms, typ.), the PWM is disabled in auto-restart mode. An input
overvoltage protection can be built by connecting a voltage divider between DIS
pin and the rectified mains. In case of non-isolated topologies, with the same
principle an output overvoltage protection can be implemented. If the disable
function is not required, DIS pin must be soldered to GND, which excludes the
function.
Direct feedback.
It is the inverting input of the internal transconductance E/A,
which is internally referenced to 1.2 V with respect to GND. In case of non-
isolated converter, the output voltage information is directly fed into the pin
through a voltage divider. In case of primary regulation, the FB voltage divider is
connected to the VCC. The E/A is disabled soldering FB to GND.
Compensation.
It is the output of the internal E/A. A compensation network is
placed between this pin and GND to achieve stability and good dynamic
performance of the control loop. In case of secondary feedback, the internal E/A
must be disabled and the COMP directly driven by the optocoupler to control the
DRAIN peak current setpoint.
MOSFET drain.
The internal high voltage current source sinks current from this
pin to charge the VCC capacitor at startup and during steady-state operation.
These pins are mechanically connected to the internal metal PAD of the
MOSFET in order to facilitate heat dissipation. On the PCB, copper area must
be placed under these pins in order to decrease the total junction-to-ambient
thermal resistance thus facilitating the power dissipation.
1
GND
2
VCC
3
DIS
4
FB
5
COMP
6 to 10
DRAIN
DocID028751 Rev 1
5/36
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
