Operating Temperature Range ......................... -40°C to +125°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
CC
= full range, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V
CC
= +5V for L/M versions, V
CC
= +3.3V for
T/S versions, V
CC
= +3V for R version, V
CC
= +2.5V for Z version, and T
A
= +25°C.) (Note 1)
PARAMETER
V
CC
Range
SYMBOL
CONDITIONS
T
A
= 0°C to +70°C
T
A
= -40°C to +105°C
T
A
= -40°C to
Supply Current
I
CC
+85°C
T
A
= +85°C to
+105°C
MAX671_L
V
CC
< 5.5V, MAX671_L/M
V
CC
< 3.6V, MAX671_R/S/T/Z
V
CC
< 5.5V, MAX671_L/M
V
CC
< 3.6V, MAX671_R/S/T/Z
T
A
= +25°C
T
A
= -40°C to +85°C
T
A
= +85°C to +105°C
T
A
= +25°C
MAX671_M
T
A
= -40°C to +85°C
T
A
= +85°C to +105°C
T
A
= +25°C
MAX671_T
Reset Threshold
V
TH
MAX671_S
T
A
= -40°C to +85°C
T
A
= +85°C to +105°C
T
A
= +25°C
T
A
= -40°C to +85°C
T
A
= +85°C to +105°C
T
A
= +25°C
MAX671_R
T
A
= -40°C to +85°C
T
A
= +85°C to +105°C
T
A
= +25°C
MAX671_Z
Reset-Threshold Tempco
V
CC
to Reset Delay (Note 2)
Reset Active Timeout Period
V
CC
= V
TH
to (V
TH
- 100 mV)
T
A
= -40°C to +85°C
T
A
= +85°C to +125°C
140
100
T
A
= -40°C to +85°C
T
A
= +85°C to +105°C
4.56
4.50
4.40
4.31
4.25
4.16
3.04
3.00
2.92
2.89
2.85
2.78
2.59
2.55
2.50
2.28
2.25
2.21
30
20
240
460
840
2.32
2.63
2.93
3.08
4.38
4.63
MIN
1.0
1.2
16
12
TYP
MAX
5.5
5.5
35
30
75
75
4.70
4.75
4.86
4.45
4.50
4.56
3.11
3.15
3.23
2.96
3.00
3.08
2.66
2.70
2.76
2.35
2.38
2.45
ppm/°C
µs
ms
V
µA
UNITS
V
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Maxim Integrated
│
2
MAX6711L/M/R/S/T/Z,
MAX6712L/M/R/S/T/Z,
MAX6713L/M/R/S/T/Z
Electrical Characteristics (continued)
4-Pin SC70 Microprocessor
Reset Circuits with Manual Reset Input
(V
CC
= full range, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V
CC
= +5V for L/M versions, V
CC
= +3.3V for
T/S versions, V
CC
= +3V for R version, V
CC
= +2.5V for Z version, and T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
V
CC
= V
TH
min, I
SINK
= 1.2mA,
RESET Output-Voltage Low
(MAX6711/MAX6713)
V
OL
MAX6711R/S/T/Z, MAX6713R/S/T/Z
V
CC
= V
TH
min, I
SINK
= 3.2mA,
MAX6711L/M, MAX6713L/M
V
CC
> 1.0V, I
SINK
= 50µA
V
CC
> V
TH
max, I
SOURCE
= 500µA,
RESET Output-Voltage High
(MAX6711)
V
OH
MAX6711R/S/T/Z
V
CC
> V
TH
max, I
SOURCE
= 800µA,
MAX6711L/M
V
CC
= V
TH
max, I
SINK
= 1.2mA,
MAX6712R/S/T/Z
V
CC
= V
TH
max, I
SINK
= 3.2mA, MAX6712L/M
V
OH
1.8V < V
CC
< V
TH
min, I
SOURCE
= 150µA
V
CC
> V
TH
, RESET deasserted
V
IL
V
IH
10
1
100
200
20
0.3 x V
CC
0.7 x V
CC
0.8 x V
CC
1
0.8 x V
CC
V
V
CC
x 1.5
0.3
V
0.4
V
µA
V
kW
µs
ns
ns
MIN
TYP
MAX
0.3
0.4
0.3
V
UNITS
RESET Output-Voltage Low
(MAX6712)
RESET Output-Voltage High
(MAX6712)
RESET Open-Drain Output-
Leakage Current
MR Input Threshold
MR Pull-Up Resistance
MR Minimum Pulse Width
MR Glitch Immunity
V
OL
MR to Reset Delay
Note 1:
Production testing done at T
A
= +25°C; limits over temperature guaranteed by design only.
Note 2:
RESET
output for MAX6711/MAX6713; RESET output for MAX6712.
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Maxim Integrated
│
3
MAX6711L/M/R/S/T/Z,
MAX6712L/M/R/S/T/Z,
MAX6713L/M/R/S/T/Z
Typical Operating Characteristics
4-Pin SC70 Microprocessor
Reset Circuits with Manual Reset Input
(V
CC
= full range, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V
CC
= +5V for L/M versions, V
CC
= +3.3V for
T/S versions, V
CC
= +3V for R version, V
CC
= +2.5V for Z version, and T
A
= +25°C.)
SUPPLY CURRENT vs. TEMPERATURE
(NO LOAD)
MAX6711/12/13 toc01
MAX671_R/S/T/Z
POWER-DOWN RESET DELAY vs. TEMPERATURE
MAX6711/12/13-TOC2
POWER-DOWN RESET DELAY (µs)
POWER-DOWN RESET DELAY (µs)
V
OD
= 10mV
60
V
OD
= 20mV
40
V
OD
= 10mV
SUPPLY CURRENT (µA)
MAX671_L/M, V
CC
= 5V
10
MAX671 _Z, V
CC
= 2.5V
MAX671 _R/S/T, V
CC
= 3.3V
5
MAX671 _L/M/R/S/T/Z, V
CC
= 1V
0
150
120
90
60
30
0
-40 -20
V
OD
= 100mV
V
OD
= 200mV
0
20 40 60 80
TEMPERATURE (°C)
100 120
V
OD
= 20mV
20
V
OD
= 100mV
V
OD
= 200mV
0
20
40
60
80
100 120
TEMPERATURE (°C)
-40 -20
0
20
40
60
80
100 120
0
-40 -20
TEMPERATURE (°C)
MAX6711/12/13-TOC4
V
TH
= 4.63V
POWER-UP RESET TIMEOUT (ms)
RESET THRESHOLD (V)
275
MAX671_ R/S/T/Z
250
1.000
0.999
225
MAX671_ L/M
0.998
200
-40 -20
0
20
40
60
80
100 120
-40 -20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
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Maxim Integrated
│
4
MAX6711/12/13-TOC5
300
POWER-UP RESET TIMEOUT vs.
TEMPERATURE
1.001
RESET THRESHOLD vs.
TEMPERATURE
MAX6711/12/13-TOC3
15
80
MAX671_L/M
POWER-DOWN RESET DELAY vs. TEMPERATURE
180
MAX6711L/M/R/S/T/Z,
MAX6712L/M/R/S/T/Z,
MAX6713L/M/R/S/T/Z
Pin Description
PIN
1
NAME
GND
RESET
(MAX6711/
MAX6713)
2
RESET
(MAX6712)
RESET output remains high while
V
CC
is below the reset threshold, and
for at least 140ms after V
CC
rises
above the reset threshold.
Manual Reset Input. RESET (RESET)
remains asserted as long as
MR
is
low, and for at least 140ms after
MR
is
deasserted. This active-low input has
an internal 20kW
(typ) pull-up resistor.
It can be driven from a TTL- or
CMOS- logic line, or shorted to ground
with a switch. Leave open or connect
to V
CC
if unused.
Supply Voltage (+5.0V, +3.3V, +3.0V,
or +2.5V)
Ground
RESET
output remains low while
V
CC
is below the reset threshold, and
for at least 140ms after V
CC
rises
above the reset threshold.
FUNCTION
4-Pin SC70 Microprocessor
Reset Circuits with Manual Reset Input
V
CC
MAX6711
RESET
MR
GND
R1
100k
Figure 2.
RESET
Valid to V
CC
= Ground Circuit
3
MR
least 140ms after V
CC
has risen above the reset thresh-
old. The MAX6713 uses an open-drain output, and
the MAX6711/MAX6712 have a push-pull output stage.
Connect a pull-up resistor on the MAX6713's
RESET
output to any supply between 0 and 6V.
Manual Reset Input
4
V
CC
400
MAXIMUM TRANSIENT DURATION (µs)
320
240
160
T
A
= +25C
MAX671_L/M
80
0
MAX671_R/S/T/Z
1
10
100
1000
Many µP-based systems require manual reset capabili-
ty, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. Reset remains asserted
while MR is low, and for at least 140ms after
MR
returns
high. This input has an internal 20kW pullup resistor, so
it can be left open if it is not used.
MR
can be driven
with TTL- or CMOS-logic levels, or with open-drain/col-
lector outputs. To create a manual reset function, con-
nect a normally open momentary switch from
MR
to
ground; external debounce circuitry is not required. If
MR
is driven from long cables or if the device is used in
a noisy environment, connecting a 0.1µF capacitor from
MR
to ground provides additional noise immunity.
Applications Information
Negative-Going V
CC
Transients
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, the MAX6711/
MAX6712/MAX6713 are relatively immune to short-dura-
tion negative-going V
CC
transients (glitches).
Figure 1 shows typical transient duration vs. reset com-
parator overdrive, for which the MAX6711/MAX6712/
MAX6713 do
not
generate a reset pulse. The graph was
generated using a negative-going pulse applied to V
CC
,
starting 0.5V above the actual reset threshold and end-
ing below it by the magnitude indicated (reset compar-
ator overdrive). The graph indicates the maximum pulse
width a negative-going V
CC
transient can have without
causing a reset pulse. As the magnitude of the transient
increases (goes farther below the reset threshold), the
RESET COMPARATOR OVERDRIVE, V
TH
- V
CC
(mV)
Figure 1. Maximum Transient Duration Without Causing a
Reset Pulse vs. Reset Comparator Overdrive
Detailed Description
Reset Output
A microprocessor's (µP's) reset input starts the µP in a
known state. The MAX6711/MAX6712/MAX6713 assert
reset to prevent code-execution errors during power-
up, power-down, or brownout conditions. They assert a
reset signal whenever the V
CC
supply voltage declines
below a preset threshold, keeping it asserted for at
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