IMPORTANT NOTICE
10 December 2015
1. Global joint venture starts operations as WeEn Semiconductors
Dear customer,
As from November 9th, 2015 NXP Semiconductors N.V. and Beijing JianGuang Asset
Management Co. Ltd established Bipolar Power joint venture (JV),
WeEn Semiconductors,
which
will be used in future Bipolar Power documents together with new contact details.
In this document where the previous NXP references remain, please use the new links as shown
below.
WWW
- For www.nxp.com use
www.ween-semi.com
Email
- For salesaddresses@nxp.com use
salesaddresses@ween-semi.com
For the copyright notice at the bottom of each page (or elsewhere in the document, depending
on the version) “
©
NXP Semiconductors N.V.
{year}.
All rights reserved”
becomes “
©
WeEn
Semiconductors Co., Ltd.
{year}.
All rights reserved”
If you have any questions related to this document, please contact our nearest sales office via e-
mail or phone (details via
salesaddresses@ween-semi.com).
Thank you for your cooperation and understanding,
WeEn Semiconductors
DISCRETE SEMICONDUCTORS
DATA SHEET
BT300S series
Thyristors
Product
specification
September 1997
1;3
Semiconductors
Product specification
Thyristors
BT300S series
BT300M series
GENERAL DESCRIPTION
Glass passivated thyristors in a plastic
envelope, suitable for surface
mounting, intended for use in
applications
requiring
high
bidirectional
blocking
voltage
capability and high thermal cycling
performance. Typical applications
include motor control, industrial and
domestic lighting, heating and static
switching.
QUICK REFERENCE DATA
SYMBOL
V
DRM
,
V
RRM
I
T(AV)
I
T(RMS)
I
TSM
PARAMETER
BT300S
(or BT300M)-
Repetitive peak off-state
voltages
Average on-state current
RMS on-state current
Non-repetitive peak on-state
current
MAX. MAX. MAX. UNIT
500R
500
5
8
65
600R
600
5
8
65
800R
800
5
8
65
V
A
A
A
PINNING - SOT428
PIN
Standard Alternative
NUMBER
S
M
1
2
3
tab
cathode
anode
gate
anode
gate
anode
cathode
anode
PIN CONFIGURATION
tab
SYMBOL
a
k
2
1
3
g
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
-
half sine wave; T
mb
≤
107 ˚C
all conduction angles
half sine wave; T
j
= 25 ˚C prior to
surge
t = 10 ms
t = 8.3 ms
t = 10 ms
I
TM
= 10 A; I
G
= 50 mA;
dI
G
/dt = 50 mA/μs
-
-
-
-
-
-
-
-
-
-
-
-40
-
MAX.
-500R -600R -800R
500
1
600
1
800
5
8
65
71
21
50
2
5
5
5
0.5
150
125
UNIT
V
A
A
A
A
A
2
s
A/μs
A
V
V
W
W
˚C
˚C
V
DRM
, V
RRM
Repetitive peak off-state
voltages
I
T(AV)
I
T(RMS)
I
TSM
Average on-state current
RMS on-state current
Non-repetitive peak
on-state current
I
2
t
dI
T
/dt
I
GM
V
GM
V
RGM
P
GM
P
G(AV)
T
stg
T
j
I
2
t for fusing
Repetitive rate of rise of
on-state current after
triggering
Peak gate current
Peak gate voltage
Peak reverse gate voltage
Peak gate power
Average gate power
over any 20 ms period
Storage temperature
Operating junction
temperature
1
Although not recommended, off-state voltages up to 800V may be applied without damage, but the thyristor may
switch to the on-state. The rate of rise of current should not exceed 15 A/μs.
September 1997
1
Rev 1.100
1;3
Semiconductors
Product specification
Thyristors
BT300S series
BT300M series
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
CONDITIONS
MIN.
-
-
TYP.
-
75
MAX.
2.2
-
UNIT
K/W
K/W
Thermal resistance
junction to mounting base
Thermal resistance
pcb (FR4) mounted; footprint as in Fig.14
junction to ambient
STATIC CHARACTERISTICS
T
j
= 25 ˚C unless otherwise stated
SYMBOL
I
GT
I
L
I
H
V
T
V
GT
I
D
, I
R
PARAMETER
Gate trigger current
Latching current
Holding current
On-state voltage
Gate trigger voltage
Off-state leakage current
CONDITIONS
V
D
= 12 V; I
T
= 0.1 A
V
D
= 12 V; I
GT
= 0.1 A
V
D
= 12 V; I
GT
= 0.1 A
I
T
= 12 A
V
D
= 12 V; I
T
= 0.1 A
V
D
= V
DRM(max)
; I
T
= 0.1 A; T
j
= 125 ˚C
V
D
= V
DRM(max)
; V
R
= V
RRM(max)
; T
j
= 125 ˚C
MIN.
-
-
-
-
-
0.25
-
TYP.
2
10
10
1.35
0.6
0.4
0.1
MAX.
15
40
20
1.6
1.5
-
0.5
UNIT
mA
mA
mA
V
V
V
mA
DYNAMIC CHARACTERISTICS
T
j
= 25 ˚C unless otherwise stated
SYMBOL
dV
D
/dt
PARAMETER
Critical rate of rise of
off-state voltage
Gate controlled turn-on
time
Circuit commutated
turn-off time
CONDITIONS
V
DM
= 67% V
DRM(max)
; T
j
= 125 ˚C;
exponential waveform.
Gate open circuit
R
GK
= 100
Ω
I
TM
= 10 A; V
D
= V
DRM(max)
; I
G
= 0.1 A;
dI
G
/dt = 5 A/μs
V
D
= 67% V
DRM(max)
; T
j
= 125 ˚C;
I
TM
= 12 A; V
R
= 25 V; dI
TM
/dt = 30 A/μs;
dV
D
/dt = 50 V/μs; R
GK
= 100
Ω
MIN.
TYP.
MAX.
UNIT
t
gt
t
q
50
200
-
-
100
1000
2
70
-
-
-
-
V/μs
V/μs
μs
μs
September 1997
2
Rev 1.100
1;3
Semiconductors
Product specification
Thyristors
BT300S series
BT300M series
Ptot / W
BT300
form
factor
Tmb(max) / C
a = 1.57
1.9
70
ITSM / A
BT300
IT
T
ITSM
time
8
6
conduction
angle
degrees
30
60
90
120
180
a
4
2.8
2.2
1.9
1.57
111
60
50
2.2
Tj initial = 25 C max
114.5
2.8
4
40
4
118
30
20
2
121.5
10
0
0
1
2
3
IT(AV) / A
4
5
6
125
0
1
10
100
Number of half cycles at 50Hz
1000
Fig.1. Maximum on-state dissipation, P
tot
, versus
average on-state current, I
T(AV)
, where
a = form factor = I
T(RMS)
/ I
T(AV)
.
ITSM / A
BT300
Fig.4. Maximum permissible non-repetitive peak
on-state current I
TSM
, versus number of cycles, for
sinusoidal currents, f = 50 Hz.
1000
24
20
16
IT(RMS) / A
BT150
dI
T
/dt limit
100
I TSM
T
time
12
IT
8
4
0
0.01
Tj initial = 25 C max
10
10us
100us
T/s
1ms
10ms
0.1
1
surge duration / s
10
Fig.2. Maximum permissible non-repetitive peak
on-state current I
TSM
, versus pulse width t
p
, for
sinusoidal currents, t
p
≤
10ms.
IT(RMS) / A
BT300S
Fig.5. Maximum permissible repetitive rms on-state
current I
T(RMS)
, versus surge duration, for sinusoidal
currents, f = 50 Hz; T
mb
≤
107˚C.
VGT(Tj)
VGT(25 C)
9
8
7
6
5
4
3
2
1
107 C
1.6
1.4
1.2
1
0.8
0.6
BT151
0
-50
0
50
Tmb / C
100
150
0.4
-50
0
50
Tj / C
100
150
Fig.3. Maximum permissible rms current I
T(RMS)
,
versus mounting base temperature T
mb
.
Fig.6. Normalised gate trigger voltage
V
GT
(T
j
)/ V
GT
(25˚C), versus junction temperature T
j
.
September 1997
3
Rev 1.100
FPGA/CPLD
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