74LV153
Dual 4-input multiplexer
Rev. 5 — 12 December 2011
Product data sheet
1. General description
The 74LV153 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC153 and 74HCT153.
The 74LV153 provides a dual 4-input multiplexer which selects 2 bits of data from up to
four sources selected by common data select inputs (S0, S1). The two 4-input multiplexer
circuits have individual active LOW output enable inputs (1E, 2E) which can be used to
strobe the outputs independently. The outputs (1Y, 2Y) are forced LOW when the
corresponding output enable inputs are HIGH. The 74LV153 is the logic implementation of
a 2-pole, 4-position switch, where the position of the switch, is determined by the logic
levels applied to S0 and S1. The logic equations for the outputs are:
1Y = 1E
(1I0
S1
S0 + 1I1
S1
S0 + 1I2
S1
S0 + 1I3
S1
S0)
2Y = 2E
(2I0
S1
S0 + 2I1
S1
S0 + 2I2
S1
S0 + 2I3
S1
S0)
The 74LV153 can be used to move data to a common output bus from a group of
registers. The state of the select inputs would determine the particular register from which
the data came. An alternative application is a function generator. The device can generate
two functions or three variables. This is useful for implementing highly irregular random
logic.
2. Features and benefits
Wide operating voltage: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
C
Non-inverting outputs
Separate enable input for each output
Common select inputs
Permits multiplexing from n lines to 1 line
Enable line provided for cascading (n lines to 1 line)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
NXP Semiconductors
74LV153
Dual 4-input multiplexer
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV153N
74LV153D
74LV153DB
74LV153PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
DIP16
SO16
SSOP16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT38-4
SOT109-1
SOT338-1
SOT403-1
Type number
4. Functional diagram
1
2E
1Y
6
5
4
3
6
5
4
3
10
11
12
13
14
2
14
2
1
15
1I0 1I1 1I2 1I3 2I0 2I1 2I2 2I3
S0
S1
1E
2E
1Y
7
2Y
9
001aal843
1I0
1I1
1I2
1I3
S0
S1
2I0
2I1
2I2
2I3
MUX
MUX
7
10
11
12
13
2Y
9
2E
15
001aal844
Fig 1.
Logic symbol
Fig 2.
Functional diagram
74LV153
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 12 December 2011
2 of 17
NXP Semiconductors
74LV153
Dual 4-input multiplexer
1E
1I3
1I2
1I1
1I0
S0
S1
2I3
2I2
2I1
2I0
2E
1Y
2Y
001aal845
Fig 3.
Logic diagram
5. Pinning information
5.1 Pinning
74LV153
1E
S1
1I3
1I2
1I1
1I0
1Y
GND
1
2
3
4
5
6
7
8
001aal846
16 V
CC
15 2E
14 S0
13 2I3
12 2I2
11 2I1
10 2I0
9
2Y
1E
S1
1l3
1l2
1l1
1l0
1Y
GND
1
2
3
4
5
6
7
8
001aal847
74LV153
16 V
CC
15 2E
14 S0
13 2l3
12 2l2
11 2l1
10 2l0
9
2Y
Fig 4.
Pin configuration DIP16, SO16
Fig 5.
Pin configuration (T)SSOP16
74LV153
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 12 December 2011
3 of 17
NXP Semiconductors
74LV153
Dual 4-input multiplexer
5.2 Pin description
Table 2.
Symbol
1E, 2E
S0, S1
1I0, 1I1, 1I2, 1I3
1Y
GND
2Y
2I0, 2I1, 2I2, 2I3
V
CC
Pin description
Pin
1, 15
14, 2
6, 5, 4, 3
7
8
9
10, 11, 12, 13
16
Description
output enable inputs (active LOW)
data select inputs
data inputs source 1
multiplexer output source 1
ground (0 V)
multiplexer output source 2
data inputs source 2
supply voltage
6. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
select Inputs
S0
X
L
L
H
H
L
L
H
H
S1
X
L
L
L
L
H
H
H
H
data inputs
nI0
X
L
H
X
X
X
X
X
X
nI1
X
X
X
L
H
X
X
X
X
nI2
X
X
X
X
X
L
H
X
X
nI3
X
X
X
X
X
X
X
L
H
output enable
nE
H
L
L
L
L
L
L
L
L
output
nY
L
L
H
L
H
L
H
L
H
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
Conditions
Min
0.5
-
-
-
-
50
65
Max
+4.6
20
50
25
50
-
+150
Unit
V
mA
mA
mA
mA
mA
C
74LV153
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 12 December 2011
4 of 17
NXP Semiconductors
74LV153
Dual 4-input multiplexer
Table 4.
Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
P
tot
Parameter
total power dissipation
DIP16 package
SO16 package
(T)SSOP16 package
[1]
[2]
[3]
[4]
Conditions
T
amb
=
40 C
to +125
C
[2]
[3]
[4]
Min
-
-
-
Max
750
500
500
Unit
mW
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 12 mW/K above 70
C.
P
tot
derates linearly with 8 mW/K above 70
C.
P
tot
derates linearly with 5.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
t/V
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
[1]
Conditions
[1]
Min
1.0
0
0
40
-
-
-
Typ
3.3
-
-
+25
-
-
-
Max
3.6
V
CC
V
CC
+125
500
200
100
Unit
V
V
V
C
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
74LV153
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 12 December 2011
5 of 17
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